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参数资料
| 型号： | TAS5036IPFCR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | GREEN, PLASTIC, TQFP-80 |
| 文件页数： | 21/49页 |
| 文件大小： | 716K |
| 代理商： | TAS5036IPFCR |
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Architecture Overview
23
SLES044B—November 2002
TAS5036
D7
D6
D1
D0 ACK
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Last Data Byte
A6
A5
A1
A0
R/W ACK A7
A5
A1
A0
ACK D7
D6
D1
D0 ACK
Start Condition
Acknowledge
First Data Byte
A4
A3
A6
Other
Data Bytes
Figure 2–15. Multiple Byte Write Transfer
2.5.3 Single Byte Read
As shown in Figure 2–16, a single byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, a write followed
by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory
address to be read. As a result, the read/write bit is 0. After receiving the TAS5036 address and the read/write
bit, the TAS5036 responds with an acknowledge bit. Also, after sending the internal memory address byte or
bytes, the master device transmits another start condition followed by the TAS5036 address and the read/write
bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5036 and the
read/write bit, the TAS5036 again responds with an acknowledge bit. Next, the TAS5036 transmits the data
byte from the memory address being read. After receiving the data byte, the master device transmits a not
acknowledge followed by a stop condition to complete the single byte data read transfer.
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Data Byte
D7
D6
D1
D0 ACK
I2C Device Address and
Read/Write Bit
Repeat Start Condition
Not
Acknowledge
R/W
A1
Figure 2–16. Single Byte Read
2.5.4 Multiple Byte Read
A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes
are transmitted by the TAS5036 to the master device as shown in Figure 2–17. Except for the last data byte,
the master device responds with an acknowledge bit after receiving each data byte.
A6
A0
ACK
Acknowledge
I2C Device Address and
Read/Write Bit
R/W
A6
A0 R/W ACK
A4
A0
ACK
D7
D0 ACK
Start
Condition
Stop
Condition
Acknowledge
Last Data Byte
D7
D6
D1
D0
ACK
First Data Byte
Repeat Start
Condition
Not
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Other
Data Bytes
A7
A6
A5
Figure 2–17. Multiple Byte Read
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