参数资料
型号: TAS5076PFCG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封装: GREEN, PLASTIC, TQFP-80
文件页数: 14/64页
文件大小: 873K
代理商: TAS5076PFCG4
Architecture Overview
15
SLES090A—November 2003—Revised January 2004
TAS5076
2.1.7.4
DSP Mode Timing
DSP mode timing uses LRCLK to define when data is to be transmitted for both channels. A bit clock running
at 64
× Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following
the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076
masks unused trailing data bit positions.
SCLK
LRCLK
64 SCLKS
LSB
MSB
16 Bits
Left
Channel
16 Bits
Right
Channel
32 Bits Unused
SDIN
LSB
MSB
Figure 29. DSP Format
2.2
Reset, Power Down, and Status
The reset, power-down, and status circuitry provides the necessary controls to bring the TAS5076 to the initial
inactive condition, achieve low-power standby, and report system status.
2.2.1 Reset—RESET
The TAS5076 is placed in the reset mode by setting the RESET terminal low.
RESET is an asynchronous control signal that restores the TAS5076 to its default conditions, sets the valid
16 outputs low, and places the PWM in the hard mute state. Volume is immediately set to full attenuation
(there is no ramp down).
As long as the RESET terminal is held low, the device is in the reset state. During reset, all I2C and serial data
bus operations are ignored. Table 26 shows the device output signals while RESET is active.
Upon the release of RESET, if POWER_DWN is high, the system performs a 4-ms to 5-ms device initialization
and then ramps the volume up to 0 db using a soft volume update sequence. If MCLK_IN is not active when
RESET is released high, then a 4-ms to 5-ms initialization sequence is produced once MCLK_IN becomes
active.
During device initialization all controls are reset to their initial states. Table 27 shows the control settings that
are changed during initialization.
RESET must be applied during power-up initialization or while changing the master slave clock states.
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