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参数资料
| 型号： | TAS5076PFCR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | GREEN, PLASTIC, TQFP-80 |
| 文件页数： | 8/64页 |
| 文件大小： | 873K |
| 代理商： | TAS5076PFCR |
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Architecture Overview
10
SLES090A—November 2003—Revised January 2004
TAS5076
Alternatively, the TAS5076 can be prevented from entering the latched mute state following a clock error when
the ERR_RCVRY terminal or the error recovery I2C command (register 0x03 bit D2) is active by writing 0x7F
to the individual error recovery register (0x04) and 0x84 to the feature enable register (0x1F).
Table 22. Master and Slave Clock Modes
DESCRIPTION
M_S
DBSPD
XTL_IN
(MHz)
MCLK_IN
(MHz)
SCLK
(MHz)
k
LRCLK
(kHz)
MCLK_OUT
(MHz)#
Internal PLL, master, normal speed
1
0
8.192
–
2.048
32
8.192
Internal PLL, master, normal speed
1
0
11.2896
–
2.8224
44.1
11.2896
Internal PLL, master, normal speed
1
0
12.288
–
3.072
48
12.288
Internal PLL, master, double speed
1
–
22.5792§
5.6448
88.2
22.5792
Internal PLL, master, double speed
1
–
24.576§
6.144
96
24.576
Internal PLL, master, quad speed
1
0
–
22.5792
11.2896
176.4
22.5792
Internal PLL, master, quad speed
1
0
–
24.576
12.288
192
24.576
Internal PLL, slave, normal speed
0
–
8.192§
2.0484
32
Digital GND
Internal PLL, slave, normal speed
0
–
11.2896§
2.8224
44.1
Digital GND
Internal PLL, slave, normal speed
0
–
12.288§
3.072
48
Digital GND
Internal PLL, slave, double speed
0
1
–
22.5792
5.6448
88.2
Digital GND
Internal PLL, slave, double speed
0
1
–
24.576§
6.144
96
Digital GND
Internal PLL, slave, quad speed ||
0
–
22.5792§
11.2896
176
Digital GND
Internal PLL, slave, quad speed ||
0
–
24.576§
12.288
192
Digital GND
A crystal oscillator is connected to XTL_IN.
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN_IN is provided.
§ External MCLK_IN connected to MCLK_IN_IN input
SCLK and LRCLK are outputs when M_S = 1, and inputs when M_S = 0.
# MCLK_OUT is driven low when M_S = 0.
|| Quad-speed mode is detected automatically.
kSCLK can be 48 or 64 times Fs
Table 23. LRCLK and MCLK_IN Rates
NORMAL SPEED (kHz)
DOUBLE SPEED (kHz)
QUAD SPEED (kHz)
LRCLK
1 Fs
32
44.1
48
1 Fs
64
88.2
96
1 Fs
176.4
192
MCLK_IN
256 Fs
8,192
11,289.6
12,288
256 Fs
16,384
22,579.2
24,576
128 Fs
22,579.2
24,576
2.1.5 PLL External Filter
In the TAS5076, a low-jitter PLL produces the internal timing (when in master mode), the master clock, SCLK,
and LRCLK. Connections for the PLL external filter are provided through PLL_FLT_OUT and PLL_FLT_RET
as shown in Figure 22.
PLL_FLT_OUT
TAS5076
PLL_FLT_RET
110
220 nF
22 nF
Figure 22. PLL External Filter
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