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参数资料
| 型号： | TAS5101IDAPRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32 |
| 封装： | POWERPAD, PLASTIC, MO-153, HTSSOP-32 |
| 文件页数： | 9/14页 |
| 文件大小： | 185K |
| 代理商： | TAS5101IDAPRG4 |
TAS5101
SLES039 – JUNE 2002
4
www.ti.com
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
BIAS_A
11
I
Connect external resistor to DVSS. See application note SLAA117
BIAS_B
12
I
Connect external resistor to DVSS. See application note SLAA117
BOOTSTRAPA
30
O
Bootstrap capacitor pin for H-bridge A
BOOTSTRAPB
19
O
Bootstrap capacitor pin for H-bridge B
DVDD
6
I
3.3-V digital voltage supply for logic
DVSS
7, 8, 9
I
Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not
connected externally to PVSS. See Figure 5.
ERR1
3
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
ERR0
4
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
LDROUTA
31
O
Low voltage drop-out regulator output A (not to be used to supply current to external circuitry)
LDROUTB
18
O
Low voltage drop-out regulator output B (not to be used to supply current to external circuitry)
OUTPUTA
26, 27
O
H-bridge output A
OUTPUTB
22, 23
O
H-bridge output B
PVDDA1
28, 29
I
High voltage power supply, H-bridge A
PVDDA2
32
I
High voltage power supply for low-dropout voltage regulator A-side
PVDDB1
20, 21
I
High voltage power supply, H-bridge B
PVDDB2
17
I
High voltage power supply for low-dropout voltage regulator B-side
PVSS
24, 25
I
High voltage power supply ground
HiZ
13
I
HiZ = 0, when asserted, the H-bridge output is set to high-impedance mode
PWM_AP
1
I
PWM input A(+)
PWM_AM
2
I
PWM input A(–)
PWM_BP
16
I
PWM input B(+)
PWM_BM
15
I
PWM input B(–)
RESET
14
I
Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low
output state. Asserting the RESET signal low causes all fault conditions to be cleared.
SHUTDOWN
5
O
Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0. The shutdown
condition can be cleared by asserting the RESET signal. This output is open drain with internal
pullup resistor.
VRFILT
10
O
A filter capacitor should be added between VRFILT and DVSS pins.
NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5010 output pins, and never
left floating. Floating PWM input pins will cause an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output
devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires
and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same
node, respectively.
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