参数资料
型号: TAS5103DAPG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 音频/视频放大
英文描述: 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32
封装: GREEN, PLASTIC, HTSSOP-32
文件页数: 11/25页
文件大小: 1335K
代理商: TAS5103DAPG4
Overtemperature Protection
Use of TAS5102/3 in High-Modulation-Index
Undervoltage Protection (UVP) and Power-On
DEVICE RESET
Overcurrent (OC) Protection With Current
www.ti.com .............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
condition has been removed. For highest possible
reliability,
recovering
from
an
overcurrent
fault
The
TAS5102/3
has
a
two-level
requires external reset of the device (see the Device
temperature-protection
system
that
asserts
an
Reset section of this data sheet) no sooner than 300
active-high warning signal (OTW) when the device
ms after the shutdown.
junction temperature exceeds 125°C (nominal) and, if
the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown,
Capable Systems
resulting in all half-bridge outputs being set in the
This device requires at least 50 ns of low time on the
high-impedance
(Hi-Z)
state
and
FAULT
being
output per 384-kHz PWM frame rate in order to keep
asserted low. OTE is latched in this case. To clear
the bootstrap capacitors charged. As an example, if
the OTE latch, RESET must be asserted. Thereafter,
the modulation index is set to 99.2% in the TAS5086,
the device resumes normal operation.
this setting allows PWM pulse durations down to 20
ns. This signal, which does not meet the 50-ns
Reset (POR)
requirement, is sent to the PWM_X pin, and this
low-state pulse time does not allow the bootstrap
The UVP and POR circuits of the TAS5102/3 fully
capacitor to stay charged. In this situation, the low
protect
the
device
in
any
power-up/down
and
voltage across the bootstrap capacitor can cause the
brownout situation. While powering up, the POR
bootstrap UVP circuitry to activate and shutdown the
circuit resets the overload circuit (OLP) and ensures
device. The TAS5102/3 device requires limiting the
that all circuits are fully operational when the
TAS5086 modulation index to 96.1% to keep the
GVDD_XY and VREG supply voltages reach 5.7 V
bootstrap capacitor charged under all signals and
(typical) and 2.7 V, respectively. Although GVDD_XY
loads.
and VREG are independently monitored, a supply
voltage drop below the UVP threshold on VREG or
Therefore, TI strongly recommends using a TI PWM
either GVDD_XY pin results in all half-bridge outputs
processor, such as TAS5508 or TAS5086, with the
immediately being set in the high-impedance (Hi-Z)
modulation index set at 96.1% to interface with
state and FAULT being asserted low. The device
TAS5102/3. This is done by writing 0x04 to the
automatically resumes operation when all supply
Modulation Limit Register (0x10) in the TAS5086 or
voltages have increased above the UVP threshold.
0x04 to the Modulation Limit Register (0x16) in the
TAS5508.
One reset pin is provided for control of half-bridges
Limiting
A/B/C/D. When RESET is asserted low, all four
The device has independent, fast-reacting current
power-stage FETs in half-bridges A, B, C, and D are
detectors on all high-side and low-side power-stage
forced into a high-impedance (Hi-Z) state. Thus, the
FETs. The detector outputs are closely monitored by
reset pin is well suited for hard-muting the power
two protection systems. The first protection system
stage if needed.
controls the power stage in order to prevent the
In BTL modes, to accommodate bootstrap charging
output current further increasing, i.e., it performs a
prior to switching start, asserting the reset input low
cycle-by-cycle current-limiting function, rather than
enables weak pulldown of the half-bridge outputs. In
prematurely shutting down during combinations of
the SE mode, the weak pulldowns are not enabled,
high-level music transients and extreme speaker load
and it is therefore recommended to ensure bootstrap
impedance
drops.
If
the
high-current
condition
capacitor charging by providing a low pulse on the
situation persists, i.e., the power stage is being
PWM inputs when reset is asserted high.
overloaded, a second protection system triggers a
latching shutdown, resulting in the power stage being
Asserting the reset input low removes any fault
set in the high-impedance (Hi-Z) state. Current
information to be signaled on the FAULT output, i.e.,
limiting
and
overcurrent
protection
are
not
FAULT is forced high.
independent
for
half-bridges
A
and
B
and,
A rising-edge transition on the reset input allows the
respectively, C and D. That is, if the bridge-tied load
device to resume operation after an overcurrent fault.
between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D are shut down.
The overcurrent protection threshold is set by a
resistor to ground from the OC_ADJ pin. A value of
22k
will result in an overcurrent threshold of 4.5 A.
Copyright 2008, Texas Instruments Incorporated
19
Product Folder Link(s): TAS5102 TAS5103
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