参数资料
型号: TAS5110ADADR
厂商: TEXAS INSTRUMENTS INC
元件分类: 音频/视频放大
英文描述: 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32
封装: GREEN, PLASTIC, HTSSOP-32
文件页数: 14/18页
文件大小: 215K
代理商: TAS5110ADADR
TAS5110A
SLES079A – APRIL 2003 – REVISED MAY 2003
www.ti.com
5
Terminal Functions
TERMINAL
NAME
DAD
NO.
I/O
DESCRIPTION
BIAS_A
6
I
Connect external resistor to DVSS.
BIAS_B
5
I
Connect external resistor to DVSS.
BOOTSTRAPA
19
O
Bootstrap capacitor pin for H-bridge A
BOOTSTRAPB
30
O
Bootstrap capacitor pin for H-bridge B
DVDD
11
3.3-V digital voltage supply for logic
DVSS
8, 9,
10
Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not
connected externally to PVSS. See Figure 5.
ERR1
14
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
ERR0
13
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
LDROUTA
18
O
Low-voltage drop-out regulator output A (not to be used to supply current to external circuitry)
LDROUTB
31
O
Low-voltage drop-out regulator output B (not to be used to supply current to external circuitry)
OUTPUTA
22, 23
O
H-bridge output A
OUTPUTB
26, 27
O
H-bridge output B
PVDDA1
20, 21
High-voltage power supply, H-bridge A
PVDDA2
17
High-voltage power supply for low-dropout voltage regulator A-side
PVDDB1
28, 29
High-voltage power supply, H-bridge B
PVDDB2
32
High-voltage power supply for low-dropout voltage regulator B-side
PVSS
24, 25
High-voltage power supply ground
PWDN
4
I
Power down = 0, normal mode = 1
PWM_AM
15
I
PWM input A(–)
PWM_AP
16
I
PWM input A(+)
PWM_BP
1
I
PWM input B(+)
PWM_BM
2
I
PWM input B(–)
RESET
3
I
Reset and mute mode = 0, normal mode = 1; when in reset mode, H-bridge MOSFETs are in low-low
output state. Asserting the RESET signal low causes all fault conditions to be cleared.
SHUTDOWN
12
O
Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0; when device is in
shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be
cleared by asserting the RESET signal. This output is open drain with internal pullup resistor.
VRFILT
7
O
A filter capacitor must be added between the VRFILT and DVSS pins.
NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins and never
left floating. Floating PWM input pins cause an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively. Both PVSS pins must also beconnectedtogetherexternally. These multiple pins are for the high-current DMOS output devices.
Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause
the device to fail. All electrical characteristics are specified and measured with all of the multiple pins of each type connected to a single node.
相关PDF资料
PDF描述
TAS5110ADAD 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32
TAS5110ADADG4 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32
TAS5110ADAPR 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32
TAS5110ADAP 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32
TAS5110DADG4 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32
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