参数资料
型号: TAS5121IDKDE4
厂商: TEXAS INSTRUMENTS INC
元件分类: 音频/视频放大
英文描述: 100 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO36
封装: GREEN, PLASTIC, HSSOP-36
文件页数: 2/22页
文件大小: 632K
代理商: TAS5121IDKDE4
www.ti.com
POWERING DOWN
PRECAUTION
CONTROL I/O
SHUTDOWN PIN: SD
TAS5121I
SLES122 – SEPTEMBER 2004
THEORY OF OPERATION (continued)
low-side MOSFET in the A half-bridge is not conducting. Because the source of the high-side MOSFET is
referenced to the drain of the low-side MOSFET, a bootstrapped capacitor is used to eliminate the need for
additional high-voltage power supplies. Under this condition, the opposite is true for the B half-bridge of the
output H-bridge. The low-side MOSFET in the B half-bridge conducts while the high-side MOSFET is not
conducting; therefore, the load connected between the OUT_A and OUT_B pins has PVDD applied to it from the
A side while ground is applied from the B side for the period of time PWM_AP is high and PWM_BP is low.
Furthermore, when the PWM signals change to the condition where PWM_AP is low and PWM_BP is high, the
opposite condition exists.
A constant high level is not permitted on the PWM inputs. This condition causes the BST capacitors to discharge
and can cause device damage.
A digitally controlled dead-time circuit controls the transitions between the high-side and low-side MOSFETs to
ensure that both devices in each half-bridge are not conducting simultaneously.
For power down of the TAS5121I, an opposite approach is necessary. The RESET must be asserted LOW
before the valid PWM signal is removed.
The TAS5121I must always start up in the high-impedance (Hi-Z) state. In this state, the BST capacitor is
precharged by a resistor on each PWM output node to ground. See Typical Application Configuration Used With
TAS5026 PWM Processor. This ensures that the TAS5121I is ready for receiving PWM pulses, indicating either
HIGH- or LOW-side turnon after RESET is deasserted to the power stage.
With the following pulldown resistor and BST capacitor size, the BST charge time is:
C = 33 nF, R = 4.7 k
R
× C × 5 = 775.5 s
After GVDD has been applied, it takes approximately 800
s to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms, the power-stage BST is charged and ready. RESET can
now be released if the PWM modulator is ready and is streaming valid PWM signals to the device. Valid PWM
signals are switching PWM signals with a frequency between 350-400 kHz. A constant HIGH level on PWM+
forces the high-side MOSFET ON until it eventually runs out of BST capacitor energy. Putting the device in this
condition should be avoided.
In practice, this means that the DVDD-to-PWM processor (modulator) should be stable, and initialization should
be completed before RESET is deasserted to the TAS5121I.
The SD pin functions as an output pin and is intended for protection-mode signaling to, for example, a controller
or other front-end device. The pin is open-drain with an internal pullup to DVDD.
The logic output is, as shown in Table 2, a combination of the device state and RESET input.
Table 2. Error Indication
SD
RESET
DESCRIPTION
0
Reserved
0
1
Device in protection mode, i.e., UVP and/or OC and/or OT error
1(1)
0
Device set high-impedance (Hi-Z), SD forced high
1
Normal operation
(1)
SD is independent from RESET. This is desirable to maintain compatibility with some TI PWM modulators.
10
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TAS5121IDKDRE4 100 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO36
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