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参数资料
| 型号： | TAS5132DDVRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO44 |
| 封装： | GREEN, PLASTIC, HTSSOP-44 |
| 文件页数： | 10/26页 |
| 文件大小： | 574K |
| 代理商： | TAS5132DDVRG4 |
www.ti.com
THEORY OF OPERATION
POWER SUPPLIES
SYSTEM POWER-UP/POWER-DOWN
Powering Up
Powering Down
SLES190 – DECEMBER 2006
ceramic capacitor placed as close as possible to
each supply pin. It is recommended to follow the
PCB layout of the TAS5132 reference design. For
To facilitate system design, the TAS5132 needs only
additional
information
on
recommended
power
a 12-V supply in addition to the (typical) 18-V
supply and required components, see the application
power-stage supply. An internal voltage regulator
diagrams given previously in this data sheet.
provides suitable voltage levels for the digital and
The 12-V supply should be from a low-noise,
low-voltage analog circuitry. Additionally, all circuitry
low-output-impedance voltage regulator. Likewise,
requiring a floating voltage supply, e.g., the high-side
the 18-V power-stage supply is assumed to have low
gate drive, is accommodated by built-in bootstrap
output impedance and low noise. The power-supply
circuitry requiring only a few external capacitors.
sequence is not critical as facilitated by the internal
In
order
to
provide
outstanding
electrical
and
power-on-reset circuit. Moreover, the TAS5132 is
acoustical characteristics, the PWM signal path
fully protected against erroneous power-stage turnon
including gate drive and output stage is designed as
due to parasitic gate charging.
identical, independent half-bridges. For this reason,
each half-bridge has separate gate drive supply
(GVDD_X),
bootstrap
pins
(BST_X),
and
SEQUENCE
power-stage supply pins (PVDD_X). Furthermore, an
additional pin (VDD) is provided as supply for all
common circuits. These RC filters provide the
recommended
high-frequency
isolation.
Special
The
TAS5132
does
not
require
a
power-up
attention should be paid to placing all decoupling
sequence. The outputs of the H-bridges remain in a
capacitors as close to their associated pins as
low-impedance state until the gate-drive supply
possible. In general, inductance between the power
voltage (GVDD_X) and VDD voltage are above the
supply pins and decoupling capacitors must be
undervoltage protection (UVP) voltage threshold (see
avoided. (See reference board documentation for
the Electrical Characteristics section of this data
additional information.)
sheet). Although not specifically required, it is
recommended to hold RESET_AB and RESET_CD
For a properly functioning bootstrap circuit, a small
in a low state while powering up the device. This
ceramic capacitor must be connected from each
allows an internal circuit to charge the external
bootstrap pin (BST_X) to the power-stage output pin
bootstrap capacitors by enabling a weak pulldown of
(OUT_X). When the power-stage output is low, the
the half-bridge output. The output impedance is
bootstrap capacitor is charged through an internal
approximately 3K
under this condition, unless
diode connected between the gate-drive power--
mode 1, 0, 0 (Single-ended Mode), is used. This
supply pin (GVDD_X) and the bootstrap pin. When
means that the TAS5132 should be held in reset for
the
power-stage
output
is
high,
the
bootstrap
at least 200
S to ensure that the bootstrap
capacitor potential is shifted above the output
capacitors are charged. This also assumes that the
potential and thus provides a suitable voltage supply
recommended 0.033-
F bootstrap capacitors are
for the high-side gate driver. In an application with
used. Changes to bootstrap capacitor values will
PWM switching frequencies in the range from 352
change the bootstrap capacitor charge time.
kHz to 384 kHz, it is recommended to use 33-nF
ceramic capacitors, size 0603 or 0805, for the
When the TAS5132 is being used with TI PWM
bootstrap supply. These 33-nF capacitors ensure
modulators such as
the
TAS5086,
no
special
sufficient energy storage, even during minimal PWM
attention to the state of RESET_AB and RESET_CD
duty cycles, to keep the high-side power stage FET
is required, provided that the chipset is configured as
(LDMOS) fully turned on during the remaining part of
recommended.
the PWM cycle. In an application running at a
reduced switching frequency, generally 192 kHz, the
bootstrap capacitor might need to be increased in
The TAS5132 does not require a power-down
value.
sequence. The device remains fully operational as
Special attention should be paid to the power-stage
long as the gate-drive supply voltage and VDD
power supply; this includes component selection,
voltage are above the undervoltage protection (UVP)
PCB placement, and routing. As indicated, each
voltage threshold (see the Electrical Characteristics
half-bridge has independent power-stage supply pins
section of this data sheet). Although not specifically
(PVDD_X). For optimal electrical performance, EMI
required, it is a good practice to hold RESET_AB
compliance, and system reliability, it is important that
and RESET_CD low during power down, thus
each PVDD_X pin is decoupled with a 100-nF
preventing audible artifacts, including pops or clicks.
18
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