参数资料
型号: TAS5152DKD
厂商: TEXAS INSTRUMENTS INC
元件分类: 音频/视频放大
英文描述: 240 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO36
封装: GREEN, PLASTIC, HSSOP-36
文件页数: 15/29页
文件大小: 681K
代理商: TAS5152DKD
TAS5152
SLES127A FEBRUARY 2005 REVISED NOVEMBER 2005
www.ti.com
22
Unfortunately, most inductors have decreasing inductance
with increasing temperature and increasing current
(saturation). To some degree, an increase in temperature
naturally occurs when operating at high output currents,
due to core losses and the DC resistance of the inductor’s
copper winding. A thorough analysis of inductor saturation
and thermal properties is strongly recommended.
Setting the OC threshold too low might cause issues such
as lack of enough output power and/or unexpected
shutdowns due to too-sensitive overload detection.
In general, it is recommended to follow closely the external
component selection and PCB layout as given in the
Application section.
For added flexibility, the OC threshold is programmable
within a limited range using a single external resistor
connected between the OC_ADJ pin and AGND. (See the
Electrical Characteristics section of this data sheet for
information on the correlation between programming-
resistor value and the OC threshold.) It should be noted
that a properly functioning overcurrent detector assumes
the presence of a properly designed demodulation filter at
the power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage but
only on the speaker terminals (after the demodulation
filter). It is required to follow certain guidelines when
selecting
the
OC
threshold
and
an
appropriate
demodulation inductor:
OC-Adjust Resistor Values
(k
W)
Max. Current Before OC
Occurs (A)
15
10.8
22
9.4
27
8.6
39
6.4
47
6
69
4.7
Overtemperature Protection
The TAS5152 has a two-level temperature-protection
system that asserts an active-low warning signal (OTW)
when the device junction temperature exceeds 125
°C
(nominal) and, if the device junction temperature exceeds
155
°C (nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance state (Hi-Z) and SD being asserted low.
OTE is latched in this case. To clear the OTE latch, both
RESET_AB
and
RESET_CD
must
be
asserted.
Thereafter, the device resumes normal operation.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the TAS5152 fully protect the
device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload
circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages
reach 9.8 V (typical). Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in all
half-bridge outputs
immediately
being
set
in
the
high-impedance state (Hi-Z) and SD being asserted low.
The device automatically resumes operation when all
supply voltages have increased above the UVP threshold.
DEVICE RESET
Two reset pins are provided for independent control of
half-bridges A/B and C/D. When RESET_AB is asserted
low, all four power-stage FETs in half-bridges A and B are
forced into a high-impedance state (Hi-Z). Likewise,
asserting RESET_CD low forces all four power-stage
FETs in half-bridges C and D into a high-impedance state.
Thus, both reset pins are well suited for hard-muting the
power stage if needed.
In BTL modes, to accommodate bootstrap charging prior
to switching start, asserting the reset inputs low enables
weak pulldown of the half-bridge outputs. In the SE mode,
the weak pulldowns are not enabled, and it is therefore
recommended to ensure bootstrap capacitor charging by
providing a low pulse on the PWM inputs when reset is
asserted high.
Asserting either reset input low removes any fault
information to be signalled on the SD output, i.e., SD is
forced high.
A rising-edge transition on either reset input allows the
device to resume operation after an overload fault.
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