参数资料
型号: TAS5414TDKDRMQ1G4
厂商: TEXAS INSTRUMENTS INC
元件分类: 音频/视频放大
英文描述: 116 W, 4 CHANNEL, AUDIO AMPLIFIER, PDSO36
封装: GREEN, PLASTIC, HSSOP-36
文件页数: 15/43页
文件大小: 978K
代理商: TAS5414TDKDRMQ1G4
www.ti.com
Random Read
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
D7
D6
D1
D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/W
A1
RepeatStart
Condition
T0036-03
Sequential Read
A6
A0
ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/W
A6
A0
R/W ACK
A0 ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress
OtherDataBytes
A7
A6
A5
D7
D0 ACK
Acknowledge
D7
D0
T0036-04
SLOS514A – FEBRUARY 2007 – REVISED JULY 2007
As shown in Figure 19, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write
bit, the TAS5414 or TAS5424 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5414 or TAS5424
address and the read/write bit again. This time the read/write bit is a 1, indicating a read transfer. After receiving
the address and the read/write bit, the TAS5414 or TAS5424 again responds with an acknowledge bit. Next, the
TAS5414 or TAS5424 transmits the data byte from the memory address being read. After receiving the data
byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte
data-read transfer.
Figure 19. Random Read Transfer
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the TAS5414 or TAS5424 to the master device as shown in Figure 20. Except for the last data
byte, the master device responds with an acknowledge bit after receiving each data byte and automatically
increments the I2C subaddress by one. Note: The fault registers do not have sequential read capabilities.
Figure 20. Sequential Read Transfer
22
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