参数资料
型号: TAS5424ATPHDMQ1
厂商: TEXAS INSTRUMENTS INC
元件分类: 音频/视频放大
英文描述: 116 W, 4 CHANNEL, AUDIO AMPLIFIER, PQFP64
封装: PLASTIC, HTQFP-64
文件页数: 15/51页
文件大小: 1422K
代理商: TAS5424ATPHDMQ1
7-BitSlave Address
R/
W
8-BitRegister Address(N)
A
8-BitRegisterDataFor
Address(N)
Start
Stop
SDA
SCL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
8-BitRegisterDataFor
Address(N)
A
T0035-01
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
T0036-01
D7
D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
LastDataByte
A6
A5
A1
A0 R/W ACK A7
A5
A1
A0
ACK D7
ACK
Start
Condition
Acknowledge
FirstDataByte
A4
A3
A6
OtherDataBytes
ACK
Acknowledge
D0
D7
D0
T0036-02
SLOS535B – MAY 2009 – REVISED JANUARY 2010
www.ti.com
Figure 16. Typical I2C Sequence
Use the I2C_ADDR pin (pin 2) to program the device for one of four addresses. These four addresses are
licensed I2C addresses and do not conflict with other licensed I2C audio devices. To communicate with the
TAS5414A and the TAS5424A, the I2C master uses addresses shown in Figure 16. Read and write data can be
transmitted using single-byte or multiple-byte data transfers.
Random Write
As shown in Figure 17, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the TAS5414A or TAS5424A device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the internal memory address being accessed. After
receiving the address byte, the TAS5414A or TAS5424A again responds with an acknowledge bit. Next, the
master device transmits the data byte to be written to the memory address being accessed. After receiving the
data byte, the TAS5414A or TAS5424A again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data-write transfer.
Figure 17. Random Write Transfer
Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master device to TAS5414A or TAS5424A as shown in Figure 17. After receiving each data
byte, the TAS5414A or TAS5424A responds with an acknowledge bit and the I2C subaddress is automatically
incremented by one.
Figure 18. Sequential Write Transfer
22
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5414A TAS5424A
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