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参数资料
| 型号： | TAS5508PAGG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 14/105页 |
| 文件大小： | 1286K |
| 代理商： | TAS5508PAGG4 |
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2.1.3
Terminal Descriptions
TAS5508
8-Channel Digital Audio PWM Processor
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
www.ti.com
TERMINAL
5-V
TYPE(1)
TERMINATION(2)
DESCRIPTION
TOLERANT
NAME
NO.
AVDD_PLL
9
P
3.3-V analog power supply for PLL. This terminal can be connected to the same
power source used to drive power terminal DVDD, but to achieve low PLL jitter,
this terminal should be bypassed to AVSS_PLL with a 0.1-
F low-ESR
capacitor.
AVSS
5, 6
P
Analog ground
AVSS_PLL
8
P
Analog ground for PLL. This terminal should reference the same ground as
terminal DVSS, but to achieve low PLL jitter, ground noise at this terminal must
be minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground-distribution techniques to achieve a quiet ground reference
at this terminal.
BKND_ERR
37
DI
Pullup
Active-low. A back-end error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in no change to any system parameters, with
all H-bridge drive signals going to a hard-mute (M) state.
DVDD
15, 36
P
3.3-V digital power supply
DVDD_PWM
54
P
3.3-V digital power supply for PWM
DVSS
16, 34,
P
Digital ground
35, 38
DVSS_PWM
53
P
Digital ground for PWM
HP_SEL
12
DI
5 V
Pullup
Headphone in/out selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
LRCLK
26
DI
5 V
Serial-audio data left/right clock (sampling-rate clock)
MCLK
63
DI
5 V
Pulldown
MCLK is a 3.3-V master clock input. The input frequency of this clock can range
from 4 MHz to 50 MHz.
MUTE
14
DI
5 V
Pullup
Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
OSC_CAP
18
AO
Oscillator capacitor
PDN
13
DI
5 V
Pullup
Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The internal parameters are preserved through
a power-down cycle, as long as RESET is not active. The duration for system
recovery from power down is 100 ms.
PLL_FLT_RET
2
AO
PLL external filter return
PLL_FLTM
3
AO
PLL negative input. Connected to PLL_FLT_RTN via an RC network
PLL_FLTP
4
AI
PLL positive input. Connected to PLL_FLT_RTN via an RC network
PSVC
32
O
Power-supply volume control PWM output
PWM_HPML
59
DO
PWM left-channel headphone (differential –)
PWM_HPMR
61
DO
PWM right-channel headphone (differential –)
PWM_HPPL
60
DO
PWM left-channel headphone (differential +)
PWM_HPPR
62
DO
PWM right-channel headphone (differential +)
PWM_M_1
40
DO
PWM 1 output (differential –)
PWM_M_2
42
DO
PWM 2 output (differential –)
PWM_M_3
44
DO
PWM 3 output (differential –)
PWM_M_4
46
DO
PWM 4 output (differential –)
PWM_M_5
55
DO
PWM 5 output (differential –)
PWM_M_6
57
DO
PWM 6 output (differential –)
PWM_M_7
49
DO
PWM 7 (lineout L) output (differential –)
PWM_M_8
51
DO
PWM 8 (lineout R) output (differential –)
PWM_P_1
41
DO
PWM 1 output (differential +)
PWM_P_2
43
DO
PWM 2 output (differential +)
PWM_P_3
45
DO
PWM 3 output (differential +)
(1)
Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2)
All pullups are 200-mA weak pullups and all pulldowns are 200-mA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups => logic-1 input; pulldowns => logic-0 input). Devices that drive
inputs with pullups must be able to sink 200 mA, while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 200 mA, while maintaining a logic-1 drive level.
Description
16
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