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参数资料
| 型号： | TAS5701PAP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64 |
| 封装： | 10 X 10 MM, GREEN, PLASTIC, HTQFP-64 |
| 文件页数： | 24/27页 |
| 文件大小： | 638K |
| 代理商： | TAS5701PAP |
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SLOS559A – JUNE 2008 – REVISED AUGUST 2010
www.ti.com
PIN FUNCTIONS (continued)
PIN
5-V
TERMINATION
I/O(1)
DESCRIPTION
TOLERANT
(2) (3)
NAME
NO.
BST_D
45
P
High-side bootstrap supply for half-bridge D
CONFIG_2
33
P
Pulldown
Input/output configuration. Connect this terminal directly to GND.
CONFIG_1
34
P
Pulldown
Input/output configuration. Connect this terminal directly to DVDD.
DVDD
15, 35
P
3.3-V Digital power supply
DVSS
26
P
Digital ground
DVSSO
20
P
Oscillator ground
FAULT
9
DO
Overtemperature, undervoltage, and overcurrent fault reporting.
Active low indicates fault. If high, normal operation.
FORMAT2
30
DI
Pulldown
Digital data format select MSB.
FORMAT1
31
DI
Pulldown
Digital data format select LSB.
FORMAT0
32
DI
Pulldown
Digital data format select.
GAIN_1
28
DI
5-V
MSB of gain select.
GAIN_0
29
DI
5-V
LSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain
selections.
GND
41, 42
P
Analog ground for power stage.
GVDD_AB
5
P
Gate drive voltage for half-bridges A and B (10.8 V to 13.2 V)
GVDD_CD
44
P
Gate drive voltage for half-bridges C and D (10.8 V to 13.2 V)
LRCLK
22
DI
5-V
Input serial audio data left/right clock (sampling rate clock)
MCLK
36
DI
5-V
Clock master input. The input frequency of this clock can range from
4.9 MHz to 49 MHz.
MUTE
21
DI
5-V
Pullup
Performs a soft mute of outputs, active-low. A logic low on this pin
sets the outputs equal to 50% duty cycle. A logic high on this pin
allows normal operation. The mute control provides a noiseless
volume ramp to silence. Releasing mute provides a noiseless ramp to
previous volume.
OC_ADJ
8
AO
Analog overcurrent programming. Requires 22-k
resistor to ground.
OSC_RES
19
AO
Oscillator trim resistor. Connect an 18.2-k
(1% tolerance is
required) resistor to DVSSO.
OUT_A
1, 64
O
Output, half-bridge A
OUT_B
60, 61
O
Output, half-bridge B
OUT_C
52, 53
O
Output, half-bridge C
OUT_D
48, 49
O
Output, half-bridge D
PDN
17
DI
5-V
Pullup
Power down, active-low. PDN stops all clocks, and outputs stop
switching whenever a logic low is applied. When PDN is released, the
device powers up all logic, starts all clocks, and performs a soft start
that returns to the previous configuration changes to FORMATx and
GAINx pins are ignored on PDN cycling.
PGND_AB
62, 63
P
Power ground for half-bridges A and B
PGND_CD
50, 51
P
Power ground for half-bridges C and D
PLL_FLTM
12
AO
PLL negative loop filter terminal
PLL_FLTP
13
AI
PLL positive loop filter terminal
PVDD_A
2, 3
P
Power supply input for half-bridge output A (0 V–21 V)
PVDD_B
58, 59
P
Power supply input for half-bridge output B (0 V–21 V)
PVDD_C
54, 55
P
Power supply input for half-bridge output C (0 V–21 V)
PVDD_D
46, 47
P
Power supply input for half-bridge output D(0 V–21 V)
RESET
16
DI
5-V
Pullup
Reset, active-low. A system reset is generated by applying a logic
low to this terminal. RESET is an asynchronous control signal that
sets the VALID outputs low, and places the PWM in the hard mute
state (stop switching). Gain is immediately set to full attenuation.
Upon the release of RESET, if PDN is high, the system performs a
4-ms to 5-ms device initialization and sets the gain and format to the
settings determined by the hardware pins.
6
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5701
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| TAS5701PAP | 制造商:Texas Instruments 功能描述:Audio Power Amplifier IC |
| TAS5701PAPG4 | 功能描述:音频放大器 20W stereo Dig Aud Pwr Amp RoHS:否 制造商:STMicroelectronics 产品:General Purpose Audio Amplifiers 输出类型:Digital 输出功率: THD + 噪声: 工作电源电压:3.3 V 电源电流: 最大功率耗散: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:TQFP-64 封装:Reel |
| TAS5701PAPR | 功能描述:音频放大器 20W stereo Dig Audio Pwr Amp RoHS:否 制造商:STMicroelectronics 产品:General Purpose Audio Amplifiers 输出类型:Digital 输出功率: THD + 噪声: 工作电源电压:3.3 V 电源电流: 最大功率耗散: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:TQFP-64 封装:Reel |
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