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参数资料
| 型号： | TAS5719PHPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP48 |
| 封装： | 7 X 7 MM, GREEN, PLASTIC, HTQFP-48 |
| 文件页数： | 21/67页 |
| 文件大小： | 1043K |
| 代理商： | TAS5719PHPR |
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A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
T0036-01
D7
D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
LastDataByte
A6
A5
A1
A0 R/W ACK
A7
A5
A1
A0
ACK D7
ACK
Start
Condition
Acknowledge
FirstDataByte
A4
A3
A6
OtherDataBytes
ACK
Acknowledge
D0
D7
D0
T0036-02
SLOS655A
– NOVEMBER 2010 – REVISED FEBRUARY 2011
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5717/9 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by
data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place,
and the data for all 16 subaddresses is successfully received by the TAS5717/9. For I2C sequential write
transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,
before a stop or start is transmitted, determines how many subaddresses are written. As was true for random
addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data
is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is
accepted; only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 36, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is 0. After receiving the correct I2C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the TAS5717/9 internal memory address being accessed. After receiving the address
byte, the TAS5717/9 again responds with an acknowledge bit. Next, the master device transmits the data byte to
be written to the memory address being accessed. After receiving the data byte, the TAS5717/9 again responds
with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte
data-write transfer.
Figure 36. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 37. After receiving each data byte, the
TAS5717/9 responds with an acknowledge bit.
Figure 37. Multiple-Byte Write Transfer
28
2010–2011, Texas Instruments Incorporated
相关PDF资料 |
PDF描述 |
|---|---|
| TAS5719PHP | 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP48 |
| TB1212N | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| TB1212F | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| TB1226DNG | SPECIALTY CONSUMER CIRCUIT, PDIP56 |
| TB1226DN | SPECIALTY CONSUMER CIRCUIT, PDIP56 |
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