参数资料
型号: TC1301B-SFCVMFTR
厂商: Microchip Technology Inc.
英文描述: Dual LDO with Microcontroller RESET Function
中文描述: 双路LDO稳压器与微控制器的复位功能
文件页数: 15/28页
文件大小: 890K
代理商: TC1301B-SFCVMFTR
2005 Microchip Technology Inc.
DS21798B-page 15
TC1301A/B
5.10
TC1301A SHDN2 Timing
V
OUT1
will rise independent of the level of SHDN2 for
the TC1301A. Figure 5-1 is used to define the wake-up
time from shutdown (t
WK
) and the settling time (t
S
). The
wake-up time is dependant upon the frequency of
operation. The faster the SHDN pin is pulsed, the
shorter the wake-up time will be.
FIGURE 5-1:
TC1301A Timing.
5.11
TC1301B SHDN1 / SHDN2 Timing
For the TC1301B, the SHDN1 input pin is used to
control V
OUT1
. The SHDN2 input pin is used to control
V
OUT2
, independent of the logic input on SHDN1.
FIGURE 5-2:
TC1301B Timing.
5.12
V
DET
and RESET Operation
The TC1301A/B integrates an independent voltage
reset monitor that can be used for low-battery input
voltage detection or a microprocessor Power-On Reset
(POR) function. The input voltage for the detector is
different for the TC1301A than it is for the TC1301B.
For the TC1301A, the input voltage to the detector is
pin 8 (V
DET
). For the TC1301B, the input voltage to the
detector is internally connected to the output of LDO #1
(V
OUT1
). The detected voltage is sensed and compared
to an internal threshold. When the voltage on the V
DET
pin is below the threshold voltage, the RESET output
pin is low. When the voltage on the V
DET
pin rises
above the voltage threshold, the RESET output will
remain low for typically 300 ms (RESET time-out
period). After the RESET time-out period, the RESET
output voltage will transition from the low output state
to the high output state if the detected voltage pin
remains above the threshold voltage.
The RESET output will be driven low within 180 μs of
V
DET
going below the RESET voltage threshold. The
RESET output will remain valid for detected voltages
greater than 1.2V overtemperature.
5.13
TC1301A RESET Timing
Figure 5-3 shows the RESET timing waveforms for the
TC1301A. This diagram is also used to define the
RESET active time-out period (t
RPU
) and the V
DET
RESET delay time (t
RPD
).
FIGURE 5-3:
TC1301A RESET Timing.
V
IN
SHDN2
V
OUT1
V
OUT2
t
wk
t
s
SHDN2
SHDN1
V
IN
V
OUT1
t
wk
t
s
V
OUT2
RESET Time
T
RPD
V
TH
V
DET
RESET
1V
V
OL
V
OH
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