参数资料
| 型号： | TC595002ECBTR |
| 厂商： | Microchip Technology |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO -5V .1A SOT23A3 |
| 标准包装： | 3,000 |
| 稳压器拓扑结构： | 负，固定式 |
| 输出电压： | -5V |
| 输入电压： | 可下调至-10V |
| 电压 - 压降（标准）： | 0.38V @ 100mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 100mA（最小） |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-236-3，SC-59，SOT-23-3 |
| 供应商设备封装： | SOT-23-3 |
| 包装： | 带卷 (TR) |
| 其它名称： | Q1275583 |
TC59
4.0
4.1
THERMAL CONSIDERATIONS
Power Dissipation
EQUATION 4-3:
P TOTAL = P D (Pass Device) + P D (Bias)
The amount of power dissipated internal to the low drop
out linear regulator is the sum of the power dissipation
within the linear pass device (P-Channel MOSFET),
and the quiescent current required to bias the internal
reference and error amplifier. The internal linear pass
device power dissipation is calculated multiplying the
voltage across the linear device times the current
through the device. The input and output voltages are
negative for the TC59. The power dissipation is
calculated using the absolute value of the voltage
difference between the input and output voltage.
For the TC59, the internal quiescent bias current is so
low (3 μ A typical), the P D (Bias) term of the power
dissipation equation can be ignored. The maximum
power dissipation can be estimated by using the
maximum input voltage and the minimum output
voltage to obtain a maximum voltage differential
between input and output and multiplying the maximum
voltage differential by the maximum output current.
EQUATION 4-4:
P MAX = (V IN (MAX) – V OUT (MIN) ) X I OUT (MAX)
TABLE 4-1:
MAXIMUM POWER
DISSIPATION
For example, given the following conditions:
Package Type
SOT-23-3
Maximum Power
Dissipation
150mW
V IN
V OUT
I OUT
= -7.0V ±5%
= -5.0V ±2%
= 1mA to 40mA
T AMBIENT (MAX) = 55°C
EQUATION 4-1:
P D (Pass Device) = (V IN – V OUT ) X I OUT
P MAX
P MAX
= (7V X (1.05) – (5.0V X 0.98)) X 40mA
= 98.0 milli-Watts
To determine the junction temperature of the device,
The internal power dissipation as a result of the bias
current for the LDO internal reference and error
amplifier is calculated by multiplying the ground or
quiescent current times the input voltage.
EQUATION 4-2:
P D (Bias) = V IN X I GND
The total internal power dissipation is the sum of
the thermal resistance from junction to air must be
known. The SOT-23-3 R θ JA is estimated to be
approximately 359°C/W when mounted on a 4-layer
board. The R θ JA will vary with physical layout, airflow
and other application specific conditions.
The device junction temperature is determined by
calculating the junction temperature rise above
ambient, then adding the rise to the ambient
temperature.
Equation 4-1 and Equation 4-2.
EQUATION 4-5:
JUNCTION
TEMPERATURE
(SOT-23 EXAMPLE)
T JUNCTION = P D (MAX) X R θ JA + T AMBIENT
T JUNCTION = 98.0 milli-Watts X 359°C/W + 55°C
T JUNCTION = 90.2°C
DS21438B-page 4
2002 Microchip Technology Inc.
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