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| 型号： | TC647VUATR |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, PDSO8 |
| 封装： | PLASTIC, MSOP-8 |
| 文件页数： | 26/28页 |
| 文件大小： | 478K |
| 代理商： | TC647VUATR |
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2002 Microchip Technology Inc.
DS21447C-page 7
TC647
4.0
SYSTEM BEHAVIOR
The flowcharts describing the TC647’s behavioral
algorithm are shown in Figure 4-1. They can be
summarized as follows:
4.1
Power-Up
(1) Assuming the device is not being held in shutdown
mode (VMIN > VREL)…
(2) Turn VOUT output on for 32 cycles of the PWM
clock. This ensures that the fan will start from a
dead stop.
(3) During this Start-up Timer, if a fan pulse is
detected, branch to Normal Operation; if none are
received…
(4) Activate the 32-cycle Start-up Timer one more time
and look for fan pulse; if a fan pulse is detected,
proceed to Normal Operation; if none are
received…
(5) Proceed to Fan Fault.
(6) End.
4.2
Normal Operation
Normal Operation is an endless loop which may only
be exited by entering shutdown mode or Fan Fault. The
loop can be thought of as executing at the frequency of
the oscillator and PWM.
(1) Reset the missing pulse detector.
(2) Is TC647 in shutdown? If so…
a. VOUT duty cycle goes to zero.
b. FAULT is disabled.
c. Exit the loop and wait for VMIN > VREL to resume
operation (indistinguishable from Power-up).
(3) Drive VOUT to a duty cycle proportional to greater
of VIN and VMIN on a cycle by cycle basis.
(4) If a fan pulse is detected, branch back to the start
of the loop (1).
(5) If the missing pulse detector times out …
(6) Activate the 3-cycle Diagnostic Timer and look for
pulses; if a fan pulse is detected, branch back to
the start of the loop (1); if none are received…
(7) Activate the 32-cycle Start-up Timer and look for
pulses; if a fan pulse is detected, branch back to
the start of the loop (1); if none are received…
(8) Quit Normal Operation and go to Fan Fault.
(9) End.
4.3
Fan Fault
Fan Fault is an infinite loop wherein the TC647 is
latched in shutdown mode. This mode can only be
released by a reset (i.e., VMIN being brought below
VSHDN, then above VREL, or by power cycling).
(1) While in this state, FAULT is latched on (low) and
the VOUT output is disabled.
(2) A reset sequence applied to the VMIN pin will exit
the loop to Power-up.
(3) End.
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