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| 型号： | TC7106AIPL |
| 元件分类： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40 |
| 封装： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件页数： | 6/34页 |
| 文件大小： | 482K |
| 代理商： | TC7106AIPL |
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TC7106/A/TC7107/A
DS21455D-page 14
2008 Microchip Technology Inc.
7.0
COMPONENT VALUE
SELECTION
7.1
Auto-Zero Capacitor (CAZ)
The CAZ capacitor size has some influence on system
noise. A 0.47 F capacitor is recommended for 200 mV
full scale applications where 1LSB is 100 V. A
0.047 F capacitor is adequate for 2.0V full scale
applications. A mylar type dielectric capacitor is
adequate.
7.2
Reference Voltage Capacitor
(CREF)
The reference voltage used to ramp the integrator out-
put voltage back to zero during the reference integrate
cycle is stored on CREF. A 0.1 F capacitor is
acceptable when VIN- is tied to analog common. If a
large Common mode voltage exists (VREF- – analog
common) and the application requires 200 mV full
scale, increase CREF to 1.0 F. Rollover error will be
held to less than 1/2 count. A mylar dielectric capacitor
is adequate.
7.3
Integrating Capacitor (CINT)
CINT should be selected to maximize the integrator
output voltage swing without causing output saturation.
Due to the TC7106A/TC7107A superior temperature
coefficient specification, analog common will normally
supply the differential voltage reference. For this case,
a ±2V full scale integrator output swing is satisfactory.
For 3 readings/second (FOSC = 48 kHz), a 0.22 F
value is suggested. If a different oscillator frequency is
used, CINT must be changed in inverse proportion to
maintain the nominal ±2V integrator swing.
An exact expression for CINT is:
EQUATION 7-1:
CINT must have low dielectric absorption to minimize
rollover
error.
A
polypropylene
capacitor
is
recommended.
7.4
Integrating Resistor (RINT)
The input buffer amplifier and integrator are designed
with class A output stages. The output stage idling
current is 100 A. The integrator and buffer can supply
20 A drive currents with negligible linearity errors.
RINT is chosen to remain in the output stage linear drive
region, but not so large that printed circuit board
leakage currents induce errors. For a 200 mV full scale,
RINT is 47 kΩ. 2.0V full scale requires 470 kΩ.
TABLE 7-1:
COMPONENT VALUES AND
NOMINAL FULL SCALE
VOLTAGE
7.5
Oscillator Components
ROSC (Pin 40 to Pin 39) should be 100 kΩ. COSC is
selected using the equation:
EQUATION 7-2:
Note that FOSC is divided by four to generate the
TC7106A internal control clock. The backplane drive
signal is derived by dividing FOSC by 800.
To achieve maximum rejection of 60 Hz noise pickup,
the signal integrate period should be a multiple of
60 Hz. Oscillator frequencies of 240 kHz, 120 kHz,
80 kHz, 60 kHz, 48 kHz, 40 kHz, etc. should be
selected. For 50 Hz rejection, oscillator frequencies of
200 kHz, 100 kHz, 66-2/3 kHz, 50 kHz, 40 kHz, etc.
would be suitable. Note that 40 kHz (2.5 readings/
second) will reject both 50 Hz and 60 Hz.
7.6
Reference Voltage Selection
A full scale reading (2000 counts) requires the input
signal be twice the reference voltage.
Where:
FOSC
=
Clock Frequency at Pin 38
VFS
=
Full Scale Input Voltage
RINT
=
Integrating Resistor
VINT
=
Desired Full Scale Integrator Output
Swing
C
INT
4000
()
1
F
OSC
-------------
VFS
R
INT
-----------
V
INT
------------------------------------------------------
=
Component
Value
Nominal Full Scale Voltage
200.0 mV
2.000V
CAZ
0.47 F
0.047 F
RINT
47 k
Ω
470 k
Ω
CINT
0.22 F
Note:
FOSC = 48 kHz (3 readings per sec).
Required Full Scale Voltage*
VREF
200.0 mV
100.0 mV
2.000V
1.000V
*VFS = 2VREF
F
OSC
0.45
RC
----------
=
Where:
FOSC
=48 kHz
COSC
=
100 pF
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