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| 型号： | TC7109ACKWR |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 4/28页 |
| 文件大小： | 598K |
| 代理商： | TC7109ACKWR |
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TC7109/A
DS21456B-page 12
2002 Microchip Technology Inc.
The CE/LOAD output LOW level, or LOW-to-HIGH
edge, may be used as a synchronizing signal to ensure
valid data, and the byte enable as an output may be
used as a byte identification flag. With SEND remaining
HIGH, the converter completes the output cycle using
CE/LOAD and LBEN, while the low order byte outputs
(bits 1 through 8) are activated. When both bytes are
sent, the Handshake mode is terminated. The typical
UART interfacing timing is shown in Figure 3-8.
The SEND input is used to delay portions of the
sequence, or handshake, to ensure correct data trans-
fer. This timing diagram shows an industry standard
HD6403 or CDP1854 CMOS UART to interface to
serial data channels. The SEND input to the TC7109A
is driven by the TBRE (Transmitter Buffer Register
Empty) output of the UART, and the CE/LOAD input of
the TC7109A drives the TBRL (Transmitter Buffer Reg-
ister Load) input to the UART. The eight transmitter
buffer register inputs accept the parallel data outputs.
With the UART transmitter buffer register empty, the
SEND input will be HIGH when the Handshake mode is
entered, after new data is stored. The high order byte
outputs become active and the CE/LOAD and HBEN
inputs will go LOW after SEND is sensed. When CE/
LOAD goes HIGH at the end of one clock period, the
high order byte data is clocked into the UART transmit-
ter buffer register. The UART TBRE output will go LOW,
which halts the output cycle with the HBEN output
LOW, and the high order byte outputs active. When the
UART has transferred the data to the transmitter regis-
ter and cleared the transmitter buffer register, the
TBRE returns HIGH. The high order byte outputs are
disabled on the next TC7109A internal clock HIGH-to-
LOW edge, and one-half internal clock later, the HBEN
output returns HIGH. The CE/LOAD and LBEN outputs
go LOW at the same time as the low order byte outputs
become active. When the CE/LOAD returns HIGH at
the end of one clock period, the low order data is
clocked into the UART transmitter buffer register, and
TBRE again goes LOW. The next TC7109A internal
clock HIGH-to-LOW edge will sense when TBRE
returns to a HIGH, disabling the data inputs. One-half
internal clock later, the Handshake mode is cleared,
and the CE/LOAD, HBEN and LBEN terminals return
HIGH and stay active, if MODE still remains HIGH.
Handshake output sequences may be performed on
demand by triggering the converter into Handshake
mode with a LOW-to-HIGH edge on the MODE input. A
handshake output sequence triggered is shown in
Figure 3-9. The SEND input is LOW when the con-
verter enters Handshake mode. The whole output
sequence is controlled by the SEND input, and the
sequence for the first (high order) byte is similar to the
sequence for the second byte.
Figure 3-9 also shows that the output sequence can
take longer than a conversion cycle. New data will not
be latched when the Handshake mode is still in
progress and is, therefore, lost.
3.3
Oscillator
The oscillator may be over driven, or may be operated
as an RC or crystal oscillator. The OSCILLATOR
SELECT input optimizes the internal configuration of
the oscillator for RC or crystal operation. The OSCIL-
LATOR SELECT input is provided with a pull-up resis-
tor. When the OSCILLATOR SELECT input is HIGH or
left open, the oscillator is configured for RC operation.
The internal clock will be the same frequency and
phase as the signal at the BUFFERED OSCILLATOR
OUTPUT. Connect the resistor and capacitor as in
Figure 3-5. The circuit will oscillate at a frequency given
by f = 0.45/RC. A 100k
resistor is recommended for
useful ranges of frequency. The capacitor value should
be chosen such that 2048 clock periods are close to an
integral multiple of the 60Hz period for optimum 60Hz
line rejection.
FIGURE 3-5:
TC7109A RC
OSCILLATOR
With OSCILLATOR SELECT input LOW, two on-chip
capacitors and a feedback device are added to the
oscillator. In this configuration, the oscillator will oper-
ate with most crystals in the 1MHz to 5MHz range, with
no external components (Figure 3-6). The OSCILLA-
TOR SELECT input LOW inserts a fixed 458 divider cir-
cuit between the BUFFERED OSCILLATOR OUTPUT
and the internal clock. A 3.58MHz TV crystal gives a
division ratio, providing an integration time given by:
EQUATION 3-1:
23
OSC
OUT
25
Buffered
OSC OUT
24
OSC
SEL
V+ or Open
22
OSC
IN
R
C
FOSC = 0.45/RC
t = (2048 clock periods)
= 33.18msec
58
3.58MHz
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相关代理商/技术参数 |
参数描述 |
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| TC7109ACLW | 功能描述:模数转换器 - ADC 13 Bit Fast Recovery RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TC7109ACLW713 | 功能描述:模数转换器 - ADC 13 Bit Fast Recovery RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TC7109ACPL | 功能描述:模数转换器 - ADC 13 Bit Fast Recovery RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TC7109AIJL | 功能描述:模数转换器 - ADC 13 Bit Fast Recovery RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TC7109CKW | 功能描述:模数转换器 - ADC 13 Bit Fast Recovery RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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