参数资料
型号: TC7109ACLW713
元件分类: ADC
英文描述: 1-CH 12-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44
封装: PLASTIC, LCC-44
文件页数: 5/30页
文件大小: 479K
代理商: TC7109ACLW713
2006 Microchip Technology Inc.
DS21456C-page 13
TC7109/A
FIGURE 3-5:
TC7109A RC Oscillator
With OSCILLATOR SELECT input LOW, two on-chip
capacitors and a feedback device are added to the
oscillator. In this configuration, the oscillator will oper-
ate with most crystals in the 1MHz to 5MHz range, with
no external components (Figure ). The OSCILLATOR
SELECT input LOW inserts a fixed 458 divider circuit
between the BUFFERED OSCILLATOR OUTPUT and
the internal clock. A 3.58MHz TV crystal gives a
division ratio, providing an integration time given by:
EQUATION 3-1:
FIGURE 3-6:
Crystal Oscillator
The error is less than 1% from two 60Hz periods, or
33.33msec, which will give better than 40dB, 60Hz
rejection. The converter will operate reliably at conver-
sion rates up to 30 per second, corresponding to a
clock frequency of 245.8kHz.
When the oscillator is to be over driven, the OSCILLA-
TOR OUTPUT should be left open, and the over driving
signal should be applied at the OSCILLATOR INPUT.
The internal clock will be of the same duty cycle, fre-
quency and phase as the input signal. When the
OSCILLATOR SELECT is at GND, the clock will be
1/58 of the input frequency.
FIGURE 3-7:
TC7109A Handshake with Send Input Held Positive
23
OSC
OUT
25
Buffered
OSC OUT
24
OSC
SEL
V+ or Open
22
OSC
IN
R
C
FOSC = 0.45/RC
t = (2048 clock periods)
= 33.18 msec
58
3.58 MHz
23
OSC
OUT
25
Buffered
OSC OUT
24
OSC
SEL
GND
V+
22
OSC
IN
58
Clock
Crystal
÷
= Three-State
High-Impendance
Integrator Output
Data Invalid
Data Valid
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
Send Input
CE/LOAD
HBEN
High Byte Data
LBEN
Low Byte Data
= Don't Care
= Three-State
will Pull-up
UART
Norm
Terminates
UART Mode
Zero Crossing Detected
Zero Crossing Occurs
Send Sensed
Mode Low, not
in Handshake Mode
Disables Outputs
CE/LOAD,
HBEN,
LBEN
Mode High Activates
CE/LOAD, HBEN, LBEN
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