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| 型号： | TC7117RCPL |
| 厂商： | Microchip Technology |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 3 1/2DGT LED DVR REV40DIP |
| 标准包装： | 10 |
| 显示器类型： | LED |
| 配置： | 7 段显示 |
| 数字或字符： | A/D，3.5 位数字 |
| 电流 - 电源： | 800µA |
| 电源电压： | 5V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-PDIP |
| 包装： | 管件 |
TC7116/A/TC7117/A
3.2.1
SYSTEM TIMING
To achieve maximum rejection of 60Hz pickup, the sig-
The clocking method used for the TC7116/TC7116A
and TC7117/TC7117A is shown in Figure . Three
clocking methods may be used:
nal integrate cycle should be a multiple of 60Hz. Oscil-
lator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
48kHz, 40kHz, etc. should be selected. For 50Hz rejec-
tion, oscillator frequencies of 200kHz, 100kHz,
1.
2.
3.
An external oscillator connected to Pin 40.
A crystal between Pins 39 and 40.
An RC network using all three pins.
66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings per second) will reject both
50Hz and 60Hz.
The oscillator frequency is ÷ 4 before it clocks the
decade counters. It is then further divided to form the
three convert cycle phases: Signal Integrate (1000
counts), Reference De-integrate (0 to 2000 counts),
and Auto-Zero (1000 to 3000 counts). For signals less
than full scale, auto-zero gets the unused portion of ref-
erence de-integrate. This makes a complete measure
cycle of 4000 (16,000 clock pulses), independent of
input voltage. For 3 readings per second, an oscillator
frequency of 48kHz would be used.
TC7117
TC7117A
Typical Segment Output
3.2.2 HOLD READING INPUT
When HLDR is at a logic HIGH, the latch will not be
updated. Analog-to-Digital conversions will continue,
but will not be updated until HLDR is returned to LOW.
To continuously update the display, connect to TEST
(TC7116/TC7116A) or GROUND (TC7117/TC7117A),
or disconnect. This input is CMOS compatible with
70k Ω typical resistance to TEST (TC7116/TC7116A) or
GROUND (TC7117/TC7117A).
0.5mA
V+
7-Segment
Decode
7-Segment
Decode
7-Segment
Decode
To
Segment
8mA
Digital Ground
Internal Digital Ground
Latch
Thousands
Hundreds
Tens
Units
To Switch Drivers
V+
From Comparator Output
Clock
÷ 4
Control Logic
500 Ω
35
37
V+
TEST
21
Digital
GND
40
OSC1
39
OSC2
38
OSC3
1
HLDR
~70k Ω
FIGURE 3-6:
TC7117/TC7117A Digital Section
? 2006 Microchip Technology Inc.
DS21457C-page 11
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