参数资料
型号: TC7129CKW
厂商: Microchip Technology
文件页数: 16/28页
文件大小: 0K
描述: IC ADC 4 1/2DGT LCD DVR 44-MQFP
标准包装: 96
显示器类型: LCD
配置: 7 段显示
数字或字符: A/D,4.5 位数字
电流 - 电源: 800µA
电源电压: 6 V ~ 12 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-QFP
供应商设备封装: 44-PQFP(10x10)
包装: 托盘
TC7129
4.17
LATCH/Hold
24
V+
The L/H output goes low during the last 100 cycles of
12 μA
3.2V
each conversion. This pulse latches the conversion
28
COM
data into the display driver section of the TC7129. This
pin can also be used as an input. When driven high, the
+
N
Logic
Section
5V
display will not be updated; the previous reading is
displayed. When driven low, the display reading is not
latched; the sequence counter reading will be
displayed. Since the counter is counting much faster
TC7129
N
P
36
23
DGND
V–
than the backplanes are being updated, the reading
shown in this mode is somewhat erratic.
4.18
Display Driver
The TC7129 drives a triplexed LCD with three back-
planes. The LCD can include decimal points, polarity
Figure 4-15:
Common Outputs.
Digital Ground (DGND) and
sign and annunciators for continuity and low battery.
Figure 4-16 shows the assignment of the display
segments to the backplanes and segment drive lines.
4.14
Low Battery
The backplane drive frequency is obtained by dividing
the oscillator frequency by 1200. This results in a back-
The low battery annunciator turns on when supply volt-
age between V– and V+ drops below 6.8V. The internal
zener diode has a threshold of 6.3V. When the supply
voltage drops below 6.8V, the transistor tied to V– turns
off pulling the “Low Battery” point high.
plane drive frequency of 100 Hz for 60 Hz operation
(120 kHz crystal) and 83.3 Hz for 50 Hz operation
(100 kHz crystal).
Backplane waveforms are shown in Figure 4-17.
These appear on outputs BP 1 , BP 2 , BP 3 (pins 16, 17
and 18). They remain the same, regardless of the
4.15
Sequence and Results Counter
segments being driven.
A sequence counter and associated control logic pro-
vide signals that operate the analog switches in the
integrator section. The comparator output from the inte-
grator gates the results counter. The results counter is
a six-section up/down decade counter that holds the
intermediate results from each successive integration.
Other display output lines (pins 4 through 15) have
waveforms that vary depending on the displayed
values. Figure 4-18 shows a set of waveforms for the
A, G, D outputs (pins 5, 8, 11 and 14) for several
combinations of “ON” segments.
The ANNUNCIATOR DRIVE output (pin 3) is a square
wave, running at the backplane frequency (100 Hz or
4.16
Overrange and Underrange
Outputs
83.3 Hz) with a peak-to-peak voltage equal to DGND
voltage. Connecting an annunciator to pin 3 turns it on;
connecting it to its backplane turns it off.
When the results counter holds a value greater than
±19,999, the DP 4 /OR output (Pin 20) is driven high.
When the results counter value is less than ±1000, the
DP 3 /UR output (Pin 21) is driven high. Both signals are
valid on the falling edge of LATCH/HOLD (L/H) and do
not change until the end of the next conversion cycle.
The signals are updated at the end of each conversion,
unless the L/H input (Pin 22) is held high. Pins 20 and
21 can also be used as inputs for external control of
decimal points 3 and 4. Figure 4-14 shows a schematic
of the input/output nature of these pins.
DS21459D-page 16
? 2006 Microchip Technology Inc.
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