参数资料
型号: TC7129CLW
元件分类: ADC
英文描述: 1-CH DUAL-SLOPE ADC, ACCESS, PQCC44
封装: PLASTIC, LCC-44
文件页数: 6/17页
文件大小: 185K
代理商: TC7129CLW
14
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
+
12 A
P
TC7129
LOGIC
SECTION
5V
3.2V
N
V
+
V
COM
DGND
24
28
36
23
Sequence and Results Counter
A sequence counter and associated control logic pro-
vide signals that operate the analog switches in the integra-
tor section. The comparator output from the integrator gates
the results counter. The results counter is a six-section up/
down decade counter which holds the intermediate results
from each successive integration.
Overrange and Underrange Outputs
When the results counter holds a value greater than
±19,999, the DP4/OR output (pin 20) is driven HIGH. When
the results counter value is less than
±1000, the DP3/UR
output (pin 21) is driven HIGH. Both signals are valid on the
falling edge of LATCH/HOLD (L/H) and do not change until
the end of the next conversion cycle. The signals are
updated at the end of each conversion unless the L/H input
(pin 22) is held HIGH. Pins 20 and 21 can also be used as
inputs for external control of decimal points 3 and 4. Figure
15 shows a schematic of the input/output nature of these
pins.
Latch/Hold
The L/H output goes LOW during the last 100 cycles of
each conversion. This pulse latches the conversion data into
the display driver section of the TC7129. This pin can also
be used as an input. When driven HIGH, the display will not
be updated; the previous reading is displayed. When driven
LOW, the display reading is not latched; the sequence
counter reading will be displayed. Since the counter is
counting much faster than the backplanes are being up-
dated, the reading shown in this mode is somewhat erratic.
Display Driver
The TC7129 drives a triplexed LCD with three back-
planes. The LCD can include decimal points, polarity sign,
and annunciators for continuity and low battery. Figure 17
shows the assignment of the display segments to the
backplanes and segment drive lines. The backplane drive
frequency is obtained by dividing the oscillator frequency by
1200. This results in a backplane drive frequency of 100Hz
for 60Hz operation (120 kHz crystal) and 83.3Hz for 50Hz
operation (100kHz crystal).
Backplane waveforms are shown in Figure 18. These
appear on outputs BP1, BP2, BP3 (pins 16, 17, and 18). They
remain the same regardless of the segments being driven.
Other display output lines (pins 4 through 15) have
waveforms that vary depending on the displayed values.
Figure 19 shows a set of waveforms for the A, G, D outputs
(pins 5, 8, 11, and 14) for several combinations of "ON"
segments.
TC7129
500 k
DP4/OR, PIN 20
DP3/UR, PIN 21
LATCH/HOLD PIN 22
CONTINUITY, PIN 27
Figure 15.
Input/Output Pin Schematic
Common and Digital Ground
The common and digital ground (DGND) outputs are
generated from internal zener diodes. The voltage between
V+ and DGND is the internal supply voltage for the digital
section of the TC7129. Common can source approximately
12
A; DGND has essentially no source capability.
Low Battery
The low battery annunciator turns on when supply
voltage between V+ and Vdrops below 6.8V. The internal
zener has a threshold of 6.3V. When the supply voltage
drops below 6.8V, the transistor tied to Vturns OFF, pulling
the "Low Battery" point HIGH. (See Figure 16.)
Figure 16.
Digital Ground (DGND) and Common Outputs
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