参数资料
型号: TC7129CPL
元件分类: ADC
英文描述: 1-CH DUAL-SLOPE ADC, ACCESS, PDIP40
封装: PLASTIC, DIP-40
文件页数: 2/17页
文件大小: 185K
代理商: TC7129CPL
10
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
RC Oscillator
For applications in which 3-1/2 digit (100
V) resolution
is sufficient, an RC oscillator is adequate. A recommended
value for the capacitor is 51pF. Other values can be used as
long as they are sufficiently larger than the circuit parasitic
capacitance. The resistor value is calculated from:
R =
For 120 kHz frequency and C = 51pF, the calculated
value of R is 75k
. The RC oscillator and the crystal
oscillator circuits are shown in Figure 8.
Measuring Techniques
Two important techniques are used in the TC7129:
successive integration and digital auto-zeroing. Successive
integration is a refinement to the traditional dual-slope
conversion technique.
Dual-Slope Conversion
A dual-slope conversion has two basic phases: inte-
grate and deintegrate. During the integrate phase, the input
signal is integrated for a fixed period of time; the integrated
voltage level is thus proportional to the input voltage. During
the deintegrate phase, the integrated voltage is ramped
down at a fixed slope, and a counter counts the clock cycles
until the integrator voltage crosses zero. The count is a
Figure 8. Oscillator Circuits
*
measurement of the time to ramp the integrated voltage to
zero, and is therefore proportional to the input voltage being
measured. This count can then be scaled and displayed as
a measurement of the input voltage. Figure 9 shows the
phases of the dual-slope conversion.
The dual-slope method has a fundamental limitation.
The count can only stop on a clock cycle, so that measure-
ment accuracy is limited to the clock frequency. In addition,
a delay in the zero-crossing comparator can add to the
inaccuracy. Figure 10 shows these errors in an actual
measurement.
Successive Integration
The successive integration technique picks up where
dual-slope conversion ends. The overshoot voltage shown
in Figure 10, called the "integrator residue voltage," is
measured to obtain a correction to the initial count. Figure 11
shows the cycles in a successive integration measurement.
The waveform shown is for a negative input signal. The
sequence of events during the measurement cycle is:
Phase
Description
INT1
Input signal is integrated for fixed time. (1000 clock
cycles on 2V scale, 10,000 on 200 mV)
DE1
Integrator voltage is ramped to zero. Counter counts
up until zero crossing to produce reading accurate
to 3-1/2 digits. Residue represents an overshoot of
the actual input voltage.
REST
Rest; circuit settles.
X10
Residue voltage is amplified 10 times and inverted.
DE2
Integrator voltage is ramped to zero. Counter counts
down until zero crossing to correct reading to 4-1/2
digits. Residue represents an undershoot of the
actual input voltage.
REST
Rest; circuit settles.
X10
Residue voltage is amplified 10 times and inverted.
DE3
Integrator voltage is ramped to zero. Counter counts
up until zero crossing to correct reading to 5-1/2
digits. Residue is discarded.
Figure 9. Dual-Slope Conversion
DEINTEGRATE
ZERO
CROSSING
TIME
INTEGRATE
TC7129
1
40
2
270 k
10 pF
V
+
120 kHz
5 pF
V
+
1
40
2
51 pF
75 k
0.45
freq
C
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