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参数资料
型号： TC7135C/KW
元件分类： ADC
英文描述： 1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQFP44
封装： 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MQFP-44
文件页数： 26/28页
文件大小： 443K
代理商： TC7135C/KW
2007 Microchip Technology Inc.
DS21460D-page 7
TC7135
3.2.1
SYSTEM ZERO
During this phase, errors due to buffer, integrator and
comparator offset voltages are compensated for by
charging CAZ (auto-zero capacitor) with a compensat-
ing error voltage. With a zero input voltage, the
integrator output will remain at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal
input
points
connect
to
the
ANALOG
COMMON pin. The reference capacitor charges to the
reference voltage potential through SWR. A feedback
loop, closed around the integrator and comparator,
charges the CAZ capacitor with a voltage to compen-
sate for buffer amplifier, integrator and comparator
offset voltages (see Figure 3-2).
FIGURE 3-2:
System Zero Phase.
3.2.2
ANALOG INPUT SIGNAL
INTEGRATION
The TC7135 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage
must be within the device Common mode range; -1V
from either supply rail, typically. The input signal
polarity is determined at the end of this phase.
FIGURE 3-3:
Input Signal Integration
Phase.
3.2.3
REFERENCE VOLTAGE
INTEGRATION
The previously charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero
(see Figure 3-4). The digital
reading displayed is:
EQUATION 3-3:
FIGURE 3-4:
Reference Voltage
Integration Cycle.
3.2.4
INTEGRATOR OUTPUT ZERO
This phase ensures the integrator output is at 0V when
the system zero phase is entered. It also ensures that
the true system offset voltages are compensated for.
This phase normally lasts 100 to 200 clock cycles. If an
overrange condition exists, the phase is extended to
6200 clock cycles (see Figure 3-5).
FIGURE 3-5:
Integrator Output Zero
Phase.
+
–
+
–
+IN
REF
IN
Analog
Common
IN
SWR
SWIZ SWZ
SWZ
Integrator
Switch Closed
Switch Open
SW
RI
+
Comparator
To
Section
Analog
Input Buffer
RINT
CINT
CREF
CSZ
SW
RI
-
SWI
SWZ
SW
RI
+
SW
RI
-
SWI
SW1
+
–
Digital
+
–
+
–
+IN
REF
IN
Analog
Common
IN
SWR
SWIZ SWZ
SWZ
Integrator
Switch Closed
Switch Open
SW
RI
+
Comparator
To
Section
Analog
Input Buffer
RINT
CINT
CREF
CSZ
SW
RI
-
SWI
SWZ
SW
RI
+
SW
RI
-
SWI
SW1
+
–
Digital
Reading
10 000
Differential Input
[]
V
REF
-----------------------------------------------
,
=
+
–
+
–
+IN
REF
IN
Analog
Common
IN
SWR
SWIZ SWZ
SWZ
Integrator
Switch Closed
Switch Open
SW
RI
+
Comparator
To
Section
Analog
Input Buffer
RINT
CINT
CREF
CSZ
SW
RI
-
SWI
SWZ
SW
RI
+
SW
RI
-
SWI
SW1
+
–
Digital
+
–
+
–
+IN
REF
IN
Analog
Common
IN
SWR
SWIZ SWZ
SWZ
Integrator
Switch Closed
Switch Open
SW
RI
+
Comparator
To
Section
Analog
Input Buffer
RINT
CINT
CREF
CSZ
SW
RI
-
SWI
SWZ
SW
RI
+
SW
RI
-
SWI
SW1
+
–
Digital
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