参数资料
型号: TC7135CLI713
厂商: Microchip Technology
文件页数: 11/28页
文件大小: 0K
描述: IC ADC 4 1/2DGT 28-PLCC
标准包装: 750
显示器类型: LED
配置: 7 段显示
接口: BCD
数字或字符: A/D,4.5 位数字
电流 - 电源: 1mA
电源电压: 4 V ~ 6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 28-LCC(J 形引线)
供应商设备封装: 28-PLCC
包装: 带卷 (TR)
TC7135
5.3
BUSY Output
5.6
POLARITY Output
At the beginning of the signal integration phase, BUSY
goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to the
logic ‘ 0 ’ state once the measurement cycle ends in an
overrange condition. The internal display latches are
loaded during the first clock pulse after BUSY and are
latched at the clock pulse end. The BUSY signal does
not go high at the beginning of the measurement cycle,
which starts with the auto-zero cycle.
A positive input is registered by a logic ‘ 1 ’ polarity
signal. The polarity bit is valid at the beginning of
reference integrate and remains valid until determined
during the next conversion.
The polarity bit is valid even for a zero reading. Signals
less than the converter's LSB will have the signal
polarity determined correctly. This is useful in null
applications.
5.4
OVERRANGE Output
5.7
Digit Drive Outputs
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVER-
RANGE output is set to a logic ‘ 1 ’. The OVERRANGE
output register is set when BUSY goes low and is reset
at the beginning of the next reference integration
phase.
Digit drive signals are positive-going signals. The scan
sequence is D 5 to D 1 . All positive pulses are 200 clock
pulses wide, with the exception D 5 , which is 201 clock
pulses wide.
All five digits are scanned continuously, unless an
overrange condition occurs. In an overrange c ondition,
all digit drives are held low from the final STROBE
5.5
UNDERRANGE Output
pulse until the beginning of the next reference integrate
phase. The scanning sequence is then repeated. This
If the output count is 9% of full scale or less (-1800
counts), the UNDERRANGE register bit is set at the
provides a blinking visual display indication.
end of BUSY. The bit is set low at the next signal
5.8
BCD Data Outputs
integration phase.
? 2007 Microchip Technology Inc.
The binary coded decimal (BCD) bits B 8 , B 4 , B 2 and B 1
are positive-true logic signals. The data bits become
active at the same time as the digit drive signals. In an
overrange condition, all data bits are at a logic ‘ 0 ’ state.
DS21460D-page 11
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