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参数资料
| 型号： | TC7660IJA |
| 厂商： | Microchip Technology |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC REG SWITCHD CAP INV ADJ 8CDIP |
| 标准包装： | 56 |
| 类型： | 切换式电容器（充电泵），反相 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | -1.5 V ~ -10 V |
| 输入电压： | 1.5 V ~ 10 V |
| 频率 - 开关： | 10kHz |
| 电流 - 输出： | 20mA |
| 同步整流器： | 无 |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-CDIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 供应商设备封装： | 8-CERDIP |
| 其它名称： | 158-1065 158-1065-ND |
TC7660
5.4
Changing the TC7660 Oscillator
5.5
Positive Voltage Multiplication
V OUT = 2 ? V – ? V F 1 + V F 2 ?
Frequency
The operating frequency of the TC7660 can be
changed in order to optimize the system performance.
The frequency can be increased by over-driving the
OSC input ( Figure 5-4 ). Any CMOS logic gate can be
utilized in conjunction with a 1 k ? series resistor. The
resistor is required to prevent device latch-up. While
TTL level signals can be utilized, an additional 10 k ?
pull-up resistor to V + is required. Transitions occur on
the rising edge of the clock input. The resultant output
voltage ripple frequency is one half the clock input.
Higher clock frequencies allow for the use of smaller
pump and reservoir capacitors for a given output volt-
age ripple and droop. Additionally, this allows the
TC7660 to be synchronized to an external clock,
eliminating undesirable beat frequencies.
At light loads, lowering the oscillator frequency can
increase the efficiency of the TC7660 ( Figure 5-5 ). By
lowering the oscillator frequency, the switching losses
are reduced. Refer to Figure 2-3 to determine the typi-
cal operating frequency based on the value of the
external capacitor. At lower operating frequencies, it
may be necessary to increase the values of the pump
Positive voltage multiplication can be obtained by
employing two external diodes ( Figure 5-6 ). Refer to
switch S 2 is closed, capacitor C 1 of Figure 5-6 is
charged up to a voltage of V + - V F1 , where V F1 is the
forward voltage drop of diode D 1 . During the next half
cycle, switch S 1 is closed, shifting the reference of
capacitor C 1 from GND to V + . The energy in capacitor
C 1 is transferred to capacitor C 2 through diode D 2 , pro-
ducing an output voltage of approximately:
EQUATION
+
where:
V F1 is the forward voltage drop of diode D 1
and
V F2 is the forward voltage drop of diode D 2 .
V +
and reservoir capacitors in order to maintain the
1
8
V +
1 k ?
2
7
TC7660
D 1
(2 V + ) - (2 V F )
D 2
4
5
desired output voltage ripple and output impedance.
V +
1 8
CMOS
+ GATE
10 μF 3 6
4 “1” 5 V OUT
10 μF
+
2 7 V OUT =
TC7660
3 6
+ +
C 1 C 2
FIGURE 5-6: Positive Voltage Multiplier.
5.6 Combined Negative Voltage
Conversion and Positive Supply
Multiplication
FIGURE 5-4:
External Clocking.
Simultaneous voltage inversion and positive voltage
multiplication can be obtained ( Figure 5-7 ). Capacitors
C 1
+
1
2
3
4
TC7660
8
7
6
5
V +
C OSC
C 2
+
V OUT
C 1 and C 3 perform the voltage inversion, while capaci-
tors C 2 and C 4 , plus the two diodes, perform the posi-
tive voltage multiplication. Capacitors C 1 and C 2 are
the pump capacitors, while capacitors C 3 and C 4 are
the reservoir capacitors for their respective functions.
Both functions utilize the same switches of the TC7660.
As a result, if either output is loaded, both outputs will
drop towards GND.
FIGURE 5-5:
Frequency.
DS21465C-page 8
Lowering Oscillator
? 2002-2011 Microchip Technology Inc.
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