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| 型号： | TC820C/PL |
| 元件分类： | ADC |
| 英文描述： | 1-CH 3-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40 |
| 封装： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件页数： | 14/34页 |
| 文件大小： | 435K |
| 代理商： | TC820C/PL |
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2007 Microchip Technology Inc.
DS21476C-page 21
TC820
FIGURE 5-11:
Window Comparator Logic
Probe.
5.11
External Peak Detection
The TC820 will hold the highest A/D conversion or
frequency reading indefinitely when the PKHOLD input
is connected to VDD. However, the analog peak input
must be present during the A/D converter's signal
integrate period. For slowly changing signals, such as
temperature, the peak reading will be properly
converted and held.
If rapidly changing analog signals must be held, an
external peak detector should be added. An inexpensive
circuit can be made from an op amp and a few discrete
components, as shown in Figure 5-12. The droop rate of
the external peak detector should be adjusted so that the
held voltage will not decay below the desired accuracy
level during the converter's 400 ms conversion time.
FIGURE 5-12:
External Peak Detector.
5.12
Liquid Crystal Display (LCD)
The TC820 drives a triplex (multiplexed 3:1) LCD with
three backplanes. The LCD can include decimal points,
polarity sign, and annunciators for over range, peak
hold, high and low logic levels, and low battery.
Table 5-2 shows the assignment of the display
segments to the backplanes and segment drive lines.
The backplane drive frequency is obtained by dividing
the oscillator frequency by 240.
Backplane waveforms are shown in Figure 5-13. These
appear on outputs BP1, BP2, and BP3. They remain the
same, regardless of the segments being driven.
FIGURE 5-13:
Backplane Waveforms.
Other display output lines have waveforms that vary
depending on the displays values. Figure 5-13 shows a
set of waveforms for the a, g, d outputs of one digit for
several combinations of "on" segments.
FIGURE 5-14:
Typical Display Output
Waveforms.
+
–
VDD
TC820
R1
DP1/HI
LOGIC
DP0/LO
DGND
1N4148
+9V
VL
R2
R3
1M
Ω
1M
Ω
Logic
Probe Input
Note: Select R1, R2, R3 for desired logic thresholds.
+
–
VH
VDD
TC820
+
–
VSS
VIN+
PKHOLD
0V
0.01F
Offset Null
1N4148
+9V
10k
Ω
VIN
TL061
BP1
BP2
BP3
VDD
VH
VL
VDISP
VDD
VH
VL
VDISP
VDD
VH
VL
VDISP
VDD
VH
VL
VDISP
Segment
Line
All OFF
a Segment
ON
d, g OFF
a, g ON
d OFF
All ON
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