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参数资料
| 型号： | TC820CKWTR |
| 元件分类： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 2/28页 |
| 文件大小： | 616K |
| 代理商： | TC820CKWTR |
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TC820
DS21476B-page 10
2002 Microchip Technology Inc.
3.2.3
SIGNAL INTEGRATION PHASE
Upon completion of the auto-zero phase, the auto-zero
loop is opened and the internal differential inputs con-
nect to VIN+ and VIN-. The differential input signal is
then integrated for a fixed time period, which is 2000
counts (4000 clock periods). The externally set clock
frequency is divided by two before clocking the internal
counters.
The integration time period is:
EQUATION 3-3:
The differential input voltage must be within the
device's Common mode range when the converter and
measured system share the same power supply com-
mon (ground). If the converter and measured system
do not share the same power supply common, as in
battery powered applications, VIN- shouldbetiedto
analog common.
Polarity is determined at the end of signal integration
phase. The sign bit is a "true polarity" indication, in that
signals less than 1LSB are correctly determined. This
allows precision null detection that is limited only by
device noise and auto-zero residual offsets.
3.2.4
REFERENCE INTEGRATE
(DE-INTEGRATE) PHASE
The reference capacitor, which was charged during the
auto-zero phase, is connected to the input of the inte-
grating amplifier. The internal sign logic ensures the
polarity of the reference voltage is always connected in
the phase opposite to that of the input voltage. This
causes the integrator to ramp back to zero at a constant
rate, determined by the reference potential.
The amount of time required (tDEINT) for the integrating
amplifier to reach zero is directly proportional to the
amplitude of the voltage that was put on the integrating
capacitor (VINT) during the integration phase.
EQUATION 3-4:
The digital reading displayed by the TC820 is:
The oscillator frequency is divided by 2 prior to clock-
ing the internal decade counters. The four-phase mea-
surement cycle takes a total of 8000 (4000) counts or
16,000 clock pulses. The 8000 count phase is indepen-
dent of input signal magnitude or polarity.
Each phase of the measurement cycle has the follow-
ing length:
TABLE 3-2:
MEASUREMENT CYCLE
PHASE LENGTH
Note
1:
This time period is fixed. The integration period for
theTC820 is:
tINT (TC820) = 4000/FOSC = 2000 counts.
Where FOSC is the clock oscillator frequency.
2:
Times shown are the RANGE/FREQ at logic low (normal
operation). When RANGE/FREQ is logic high, signal
integrate times are 200 counts. See Section 3.2.7,
“10:1 Range Change”.
3.2.5
INPUT OVER RANGE
When the analog input is greater than full scale, the
LCD will display "OL" and the "OVER RANGE" LCD
annunciator will be on.
3.2.6
PEAK READING HOLD
The TC820 provides the capability of holding the high-
est (or peak) reading. Connecting the PK HOLD input
to VDD enables the peak hold feature. At the end of
each conversion, the contents of the TC820 counter
are compared to the contents of the display register. If
the new reading is higher than the reading being dis-
played, the higher reading is transferred to the display
register. A "higher" reading is defined as the reading
with the higher absolute value.
The peak reading is held in the display register, so the
reading will not "droop" or slowly decay with time. The
held reading will be retained until a higher reading
occurs, the PK HOLD input is disconnected from VDD,
or power is removed.
The peak signal to be measured must be present dur-
ing the TC820 signal integrate period. The TC820 does
not perform transient peak detection of the analog input
signal. However, in many cases, such as measuring
temperature or electric motor starting current, the
TC820 "acquisition time" will not be a limitation. If true
peak detection is required, a simple circuit will suffice.
See the applications section for details.
The peak reading function is also available when the
TC820 is in the Frequency Counter mode. The counter
auto-ranging feature is disabled when peak reading
hold is selected.
tINT =
4000
FOSC
tDEINT =
RINTCINTVINT
VREF
VIN+VIN-
Digital Count = 2000
VREF
Conversion Phase
Counts
1) Auto-Zero
1500
2) Signal Integrate (Notes 1, 2)
2000
3) Reference Integrate
1 to 4001
4) Integrator Output Zero
499 to 4499
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