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| 型号： | TC835CBU |
| 元件分类： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PQFP64 |
| 封装： | PLASTIC, QFP-64 |
| 文件页数： | 4/24页 |
| 文件大小： | 543K |
| 代理商： | TC835CBU |
TC835
DS21478B-page 12
2002 Microchip Technology Inc.
5.4
OVERRANGE Output
If the input signal causes the reference voltage integra-
tion
time
to
exceed
20,000
clock
pulses,
the
OVERRANGE output is set to a logic "1." The over-
range output register is set when BUSY goes low, and
is reset at the beginning of the next reference
integration phase.
5.5
UNDERRANGE Output
If the output count is 9% of full scale or less (-1800
counts), the underrange register bit is set at the end of
BUSY. The bit is set low at the next signal integration
phase.
5.6
POLARITY Output
A positive input is registered by a logic "1" polarity
signal. The POLARITY bit is valid at the beginning of
Reference Integrate and remains valid until determined
during the next conversion.
The POLARITY bit is valid even for a zero reading.
Signals less than the converter's LSB will have the sig-
nal polarity determined correctly. This is useful in null
applications.
5.7
Digit Drive Outputs
Digit drive signals are positive going signals. The scan
sequence is D5 to D1. All positive pulses are 200 clock
pulses wide, except D
5, which is 201 clock pulses wide.
All five digits are scanned continuously, unless an over-
range condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse
until the beginning of the next reference integrate
phase. The scanning sequence is then repeated. This
provides a blinking visual display indication.
5.8
BCD Data Outputs
The binary coded decimal (BCD) bits B8,B4,B2,B1 are
positive-true logic signals. The data bits become active
simultaneously with the digit drive signals. In an
overrange condition, all data bits are at a logic "0" state.
6.0
TYPICAL APPLICATIONS
6.1
Component Value Selection
The integrating resistor is determined by the full-scale
input voltage and the output current of the buffer used
to charge the integrator capacitor. Both the buffer
amplifier and the integrator have a class A output
stage, with 100
A of quiescent current. A 20Adrive
current gives negligible linearity errors. Values of 5
A
to 40
A give good results. The exact value of an
integrating resistor for a 20
A current is easily calcu-
lated.
EQUATION 6-1:
6.1.1
INTEGRATING CAPACITOR
The product of integrating resistor and capacitor should
be selected to give the maximum voltage swing that
ensures the tolerance buildup will not saturate the inte-
grator swing (approximately 0.3V from either supply).
For ±5V supplies and ANALOG COMMON tied to sup-
ply ground, a ±3.5V to ±4V full-scale integrator swing is
adequate. A 0.10
Fto0.47F is recommended. In
general, the value of CINT is given by:
EQUATION 6-2:
A very important characteristic of the integrating capac-
itor is that it has low dielectric absorption to prevent
rollover or ratiometric errors. A good test for dielectric
absorption would be to use the capacitor with the input
tied to the reference. This ratiometric condition should
read half scale 0.9999, with any deviation probably due
to dielectric absorption. Polypropylene capacitors give
undetectable errors at reasonable cost. Polystyrene
and polycarbonate capacitors may also be used in less
critical applications.
6.1.2
AUTO ZERO AND REFERENCE
CAPACITORS
The size of the auto zero capacitor has some influence
on the noise of the system. A large capacitor reduces
the noise. The reference capacitor should be large
enough such that stray capacitance to ground from its
nodes is negligible.
The dielectric absorption of the reference capacitor and
auto zero capacitor are only important at power-on or
when the circuit is recovering from an overload.
RINT =
Full scale voltage
20
A
CINT =
[10,000 x clock period] x IINT
Integrator output voltage swing
=
(10,000) (clock period) (20
A)
Integrator output voltage swing
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