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参数资料
| 型号： | TC835CPIG |
| 元件分类： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 6/24页 |
| 文件大小： | 543K |
| 代理商： | TC835CPIG |
TC835
DS21478B-page 14
2002 Microchip Technology Inc.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators
are shown in Section 6.0, Typical Applications. The
multiplexed output means that if the display takes sig-
nificant current from the logic supply, the clock should
have good PSRR.
6.5
Zero Crossing Flip-Flop
The flip flop interrogates the data once every clock
pulse after the transients of the previous clock pulse
and half-clock pulse have died down. False zero cross-
ings caused by clock pulses are not recognized. Of
course, the flip flop delays the true zero crossing by up
to one count in every instance. If a correction were not
made, the display would always be one count too high.
Therefore, the counter is disabled for one clock pulse
at the beginning of the reference integrate (de-inte-
grate) phase. This one-count delay compensates for
the delay of the zero crossing flip flop and allows the
correct number to be latched into the display. Similarly,
a one-count delay at the beginning of auto zero gives
an overload display of 0000 instead of 0001. No delay
occurs during signal integrate, so that true ratiometric
readings result.
FIGURE 6-1:
4-1/2 DIGIT ADC MULTIPLEXED COMMON ANODE LED DISPLAY
20
19
18
17
12
23
7
8
16
15
14
13
11
2
1
3
9
10
22
6
5
4
6
2
1
7
5
9–15
16
bc
777
7
DM7447A
Blank MSD On Zero
D1 D2
D3
D4
D5
INT OUT
AZ IN
BUFF
OUT
FIN
+INPUT
–INPUT
ANALOG
COMMON
V –
REF
IN
POL
CREF-
B8
B4
B2
B1
+5V
X7
0.33
F
200kHz
+
–
Analog
Input
1
F
100k
1
F
4.7k
1
F
1
F
–5V
100k
100k
D
B
C
A
RBI
V+
CREF+
TC835
MCP1525
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