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参数资料
| 型号： | TC86R4400 |
| 厂商： | Toshiba Corporation |
| 英文描述： | RISC High Performance Microprocessor(精简指令集高性能微处理器) |
| 中文描述： | 高性能微处理器的RISC（精简指令集高性能微处理器） |
| 文件页数： | 2/4页 |
| 文件大小： | 90K |
| 代理商： | TC86R4400 |
TC86R4400 MIPS RISC Microprocessor
2
T O S H IB A A M E R IC A E L E C T R O N IC C O M P O N E N T S , IN C
.
R4400SC Microprocessor
Toshibas R4400SC 64-bit microprocessor and an advanced
operating system, like Windows NT
ability to address new expectations in the mainstream system
and high-end server/workstation market at unbeatable price/
performance points. R4400SC-based systems can run a choice
of advanced operating systems, such as Windows NT and UNIX
which protect end user software investments while also providing
an open software environment, are two important achievements
for Toshiba in meeting the mainstream and high-end PC market
needs. The R4400SC operates from 150MHz (input clock 75
MHz) to 250MHz (input clock 125MHz), and can sustain
performance in excess of 175SPECint92.
,
gives the designer the
a
R4400SC Overview
Toshibas R4400SC is a highly integrated, single-chip RISC
microprocessor designed for high-performance uniprocessor sys-
tems with secondary cache support. The R4400SC provides com-
plete application software compatibility with the MIPS R2000,
R3000, R4000, and R8000 processors. High integer performance,
as well as oating-point performance, has been achieved through
a number of techniques such as superpipelining, on-chip data and
instruction caches, a pipelined oating point unit, support for two
level cache memory and a high-performance on-chip TLB. The
R4400SC provides a compatible, timely and necessary path from
32-bit to true 64-bit computing for users and software developers.
R4400SC Features
￥ True 64-bit microprocessor with 64-bit integer and floating-
point operations, registers and virtual addresses
￥ Fully compatible with earlier 32-bit MIPS microprocessor.
￥ Dual instruction issue with no restrictions on the type of
instruction issued
￥ On-chip Memory Management Unit (MMU) containing a fully
associative TLB whose entries have a variable page size rang-
ing from 4Kbyte to 16Mbyte
￥ On-chip ANSI/IEEE-754 standard floating-point unit with
precise exceptions
￥ 32 doubleword (64-bit) general-purpose registers and 32
doubleword floating-point registers
￥ 36-bit physical address accessing 64GB of physical
memory
￥ Built in primary direct mapped caches with parity protection:
D 16KB instruction cache
D 16KB data cache
D Buffered write back with ConTgurable 4 or 8 word
line size
￥ R4400SC also has built-in direct mapped secondary cache
support:
D The secondary cache can range from 128Kbytes to
4Mbytes
D 128-bit interface to minimize cache miss latency
D Timing exibility for 128-bit secondary cache interface
D ECC protection
￥ 64-bit system interface to allow speed matching of logic and
memory components
￥ Dynamically configurable big-endian or little-endian byte
ordering
In order to achieve the high performance required in a third
generation RISC design, the TC86R4400SC exploits instruction-
level parallelism using a superpipelined micro-instruction. The
TC86R4400SC implements an 8-stage superpipeline which
places no restrictions on instruction issue. Any two instructions
can be issued each cycle under normal circumstances. Since the
superpipeline places no restrictions on the order of instruction
issue, the full beneTt of the TC86R4400SC can be realized by
existing application programs without any need for recompila-
tion. The internal pipeline of the TC86R4400SC operates at fre-
quency from 150MHz to 200MHz, which is twice the external
clock frequency.
R4400MC Microprocessor
TC86R4400MC-based multiprocessor computer systems
can run a choice of advanced operating systems, such as
Windows NT, UNIX and Univel. Protecting the end user soft-
ware investments and also providing an open software environ-
ment are two important achievements in meeting the high-end
market needs. The TC86R4400MC operates at frequencies from
150MHz internal (external clock 75MHz) to 250MHz internal
(125MHz external), and can sustain performance in excess of
175SPECint92.
R4400MC Overview
Toshiba R4400MC is a highly integrated, single-chip RISC
microprocessor designed for high-performance multiprocessing
systems. The R4400MC provides complete application-software
compatibility with the MIPS R2000, R3000, R4400 and R8000
processors. High integer performance, as well as oating-point
performance, has been achieved through a number of techniques
such as superpipelining, on-chip data and instruction caches, a
pipelined oating point unit, support for two level cache memory
and a high-performance on-chip TLB. The R4400MC provides a
compatible, timely and necessary path from 32-bit to true 64-bit
computing for users and software developers.
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