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参数资料
| 型号： | TC9028P |
| 元件分类： | 摇控器 |
| 英文描述： | INFRARED, TRANSMITTER IC, PDIP20 |
| 封装： | 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-20 |
| 文件页数： | 7/21页 |
| 文件大小： | 571K |
| 代理商： | TC9028P |
TC9028P/F
2002-01-08
15
Object Code
Flag
Function
Mnemonic
Binary
Hexadecimal
Operation
CF
SF
Cycles
ADD
A, @LR
0000
0011
03
Acc ← Acc + RAM [LR]
―
C
1
ADDC
A, @LR
0000
0100
04
Acc ← Acc + RAM [LR] + CF
C
1
ADD
A, #k
0100
kkkk
4k
Acc ← Acc + k
―
C
1
ADD
L, #k
0101
kkkk
5k
LR ← LR + k
―
C
2
SUBRC
A, @LR
0000
0101
05
Acc ← RAM [LR] Acc CF
C
1
INC
@LR
0000
1001
09
RAM [LR] ← RAM [LR] + 1
―
C
1
DEC
@LR
0000
1000
08
RAM [LR] ← RAM [LR] 1
―
C
1
INC
D
0000
1011
0B
DC ← DC + 1
―
C
1
DEC
D
0000
1010
0A
DC ← DC 1
―
C
1
AND
A, @LR
0000
00
Acc ← Acc Λ RAM [LR]
―
Z
1
OR
A, @LR
0000
0001
01
Acc ← Acc V RAM [LR]
―
Z
1
Operation
(arithmetic &
Logical)
XOR
A, @LR
0000
0010
02
Acc ← Acc
RAM [LR]
―
Z
1
CLR
@LR, b
1000
01bb
84 + b
RAM [LR] b ← 0
―
1
2
SET
@LR, b
1000
00bb
80 + b
RAM [LR] b ← 1
―
1
2
Bit
manipulation
TEST
@LR, b
1000
11bb
8C + b
SF ←
b
[LR]
RAM
―
*
2
CLR
CF
1000
1011
8B
CF ← 0
0
1
2
SET
CF
1000
1001
89
CF ← 1
1
2
Flag
manipulation
TESTP
CF
0111
77
SF ← CF
―
*
1
BSS
a
11dd
dddd
C0 + d
if SF = 1 then PC ← a else null,
a = PC9-6d
―
1
2
Branch
LD
MBR, #k
1011
kkkk
Bk
MBR ← k
―
1
CALLS
a
1010
nnnn
An
STACK ← PC, PC ← a,
a = 2n (n = 1~15)
―
2
Subroutine
RET
0110
1110
6E
PC ← STACK
―
2
HOLD
0000
0111
07
hold
―
1
CPU control
NOP
0111
1111
7F
no operation
―
1
Timer counter
control
TMRST
1000
88
reset timer counter
―
1
Note 3: C : Carry from the highest digit for addition and non-borrow to the highest digit for subtraction.
Z : Zero detection data are 1 when data transferred to the accumulator or RAM are 0000B.
* : Value specified by operation is set.
― : No flag change.
Note 4: The PC contains the address following the instruction being executed.
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