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参数资料
| 型号： | TC90A67F |
| 元件分类： | 画面叠加 |
| 英文描述： | PICTURE-IN-PICTURE IC, PQFP80 |
| 封装： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件页数： | 6/24页 |
| 文件大小： | 321K |
| 代理商： | TC90A67F |
TC90A67F
2002-02-06
14
Sub
Address
Bit
Name
Preset
Comment
D15 to D10
MTXCB
[5:0]
110001
Set RGB matrix coefficient 1.
D9 to D5
MTXCG
[24:20]
01100
Set RGB matrix coefficient 2.
1CH
D4 to D0
MTXCG
[14:10]
01010
Set RGB matrix coefficient 3.
D15, D10
YGOS [5:0]
000000
Set DC offset of sub-picture. (Y or G signal)
100000: 32 LSB, 000000: 0 LSB, 011111: 31 LSB
D9 to D5
ROS [4:0]
00000
Set DC offset of sub-picture. (R-Y or R signal)
10000: 16 LSB, 00000: 0 LSB, 01111: 15 LSB
1DH
D4 to D0
BOS [4:0]
00000
Set DC offset of sub-picture. (B-Y or B signal)
10000: 16 LSB, 00000: 0 LSB, 01111: 15 LSB
D15, D14
YSDLY [1:0]
01
Timing offset of Ys pulse. 00: 1 ck, 01: center, 10: 1 ck, 11: 2 ck (24 MHz)
D13, D12
FRAMEW
[1:0]
00
Select the side frame width of sub-picture.
00: OFF (no-frame), 01: narrow, 10: center, 11: wide
D11 to D8
FRAMEYG
[3:0]
0000
Select frame signal level of PIP. (Y or G signal)
D7 to D4
FRAMER
[3:0]
0000
Select frame signal level of PIP. (R-Y or R signal)
1EH
D3 to D0
FRAMEB
[3:0]
0000
Select frame signal level of PIP. (B-Y or B signal)
D15, D14
TYDLY [1:0]
00
Y-output signal delay for U and V output signal. (fine).
D13
0
Fix to ‘0’
D12
PMDFIX
0
Clock frequency to read from the memory.
0: auto, 1: fix
D11, D10
PMDS [1:0]
00
Select Clock frequency to read from the memory.
(active at PMDFIX
1 only) 00: 12 MHz, 01: 9 MHz, 10: 18 MHz, 11: 16 MHz
D9
OFF2527
0
Set 50 Hz/ 60 Hz-conversion mode. (VWS
1/3 mode only)
0: ON, 1: OFF
D8
SELREV
0
Set reverse mode.
0: normal, 1: reverse
D7 to D3
00000
Fix to ‘0’
D2
PFLDREV
1
Reverse PFIELD at internal circuit. 0: reverse, 1: normal
D1
CFLDREV
0
Reverse CFIELD at internal circuit. 0: normal, 1: reverse
1FH
D0
RGBON
1
Select output signal format.
0: YUV, 1: RGB
D15 to D8
CHLOADN
[7:0]
111111
10
Set clock frequency of sub-picture processing at 60 Hz system.
(set the dividing number of H-PLL)
20H
D7 to D0
CHLOADP
[7:0]
111110
01
Set clock frequency of main-picture processing at 50 Hz system.
(set the dividing number of H-PLL)
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