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参数资料
| 型号： | TC90A92AFG |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 16/34页 |
| 文件大小： | 459K |
| 代理商： | TC90A92AFG |
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TC90A92AFG
*Sub address 24h Regarding digital output
24h(D7-D4) Setting horizontal phase for HDOUT
When sync signal is the same timing as HDOUT, the difference phase is 0us.
24h(D3-D0) Setting vertical phase for VDOUT
When vertical phase is 0H, timing diagram is as below.
This is available for H,V-OUT through mode. (26h:D4=1)
*Sub address 25h(D7-D5) VPHS: Setting VDOUT phase
When H,V-OUT through mode is on, it can shift VDOUT phase to horizontal direction. (2.4us step)
*Sub address 25h(D3-D2) HDST: Setting HDOUT phase
When H,V-OUT through mode is on, it can shift HDOUT phase.
It can delay HDOUT pulse from EAV based on standard.
Regarding 525 lines system
HDOUT phase (Default)
It is 32W from first point of EAV. (1W=1/27MHz)
HD width is about 4.73us. (128ck 1ck=1/27MHz)
00:32W(default) , 01:+4ck , 10:+8ck , 11:+16ck
Regarding 625 lines system
HDOUT phase (Default)
It is 24W from first point of EAV. (1W=1/27MHz)
HD width is about 4.73us. (128ck 1ck=1/27MHz)
00:24W(default) , 01:+4ck , 10:+8ck , 11:+16ck
*Sub address 26h(D5) PFPOLE,(D2) SEL_BLK
26h(D5) Setting field polarity
When the polarity is positive, 1st field is low.
26h(D2) the disposal of blanking period
0:It is masked the signal under pedestal level.
1:Through
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gcnts
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