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参数资料
| 型号： | TC94A23F |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 15/20页 |
| 文件大小： | 339K |
| 代理商： | TC94A23F |
TC94A23F
2002-02-06
4
Block Diagram
P3-3 (ADin3)
RST
TESTM
DVSL
LO
DVRL
DVDD
RO
DVRR
DVSR
IN1 (BCKin)
IN2
P4-3 (SCK/SCL)
P4-2 (SI0/SI1/SDA)
TMAX
PDO
P2VREF
VCOF
SBOK
PVREF
SBSY
DOUT
OT22 (COFS)
OT21 (SPDA)
OT20 (SPCK)
TESTC
MVSS
MVDD
AV
SS
AV
DD
RF
CI
R
FZI
RF
RP
FEI
SB
AD
TEI
TEZ
I
FOO
FM
O
DM
O
2V
REF
SEL
TR
O
TEBC
RF
GC
V
REF
HOLD
P4-0 (ADin4/BUZR)
P3-1 (ADin1)
P3-2 (ADin2)
OT19 ( HSO )
XVSS
XO
XI
XVDD
VDD
VSS
COM
1
(OT1)
COM
2
(OT2)
COM
3
(OT3)
COM
4
(OT4)
S1
(
O
T5
)
P4-1 (SI2)
S
14
(OT18/
LRC
K
)
S
13
(OT17/
S
F
S
Y
)
S
12
(OT16/
D
A
T
A
)
S
11
(OT15/
CLC
K
)
P
8
-3
(S
18/
IP
F)
P
8
-2
(S
17/
M
B
O
V
)
P8
-1
(
S
1
6
/AO
U
T
)
P8
-0
(
S
1
5
/BC
K)
LPFN
RFI
SLCO
P3-0
INTR
P2-3 (DATAin)
P2-0 (EMPHin)
P2-1 ( HSO in)
P2-2 (LRCKin)
LPFO
MXI
MXO
P1-3
P1-0
S2
(
O
T6
)
S
10
(OT14/
ZDE
T)
X’
ta
lO
S
C
LP
F
X’tal OSC
Port1
MPX
Clock gene.
CPU clock
Timer
Interrupt
Cont.
Port4
BUZR
AD
Conv.
Serial
Interface
Port3
LCD Driver/Output Port
Port8
Bias
1
bi
tD
A
C
ZDET
PWM
CD clock
VREF
SBSY
DA
SERVO
control
Digital equalizer
Automatic adjustment
circuit
ROM
RAM
16 k SRAM
CLV
servo
VREF
Synchronous
guarantee EFM
decode
Sub code decoder
Data
slicer
VREF
PLL
TMAX
VCO
Correction circuit
A
ddres
s
AD
Digital out
Audio out
Micon interface
Data Reg (16 bit)
ROM
(16
8192 Step)
Program
Counter
Stack Reg.
(8Level)
G-Reg.
R/W Buf.
ALU
OT19-22
Po
rt
2
Power on Reset
F/F
Reset
ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF
RAM
(4
512 word)
Instruction
Decoder
SBSY
CLCK, DATA, SFSY,
LRCK, BCK, MBOV, IPF
CD Reset
P2-0~P2-3
IN1
Reset
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