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参数资料
| 型号： | TCM320AC46DW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 文件页数： | 8/19页 |
| 文件大小： | 246K |
| 代理商： | TCM320AC46DW |
TCM320AC46
GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 – D4091, JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
16
PARAMETER MEASUREMENT INFORMATION
N–1
N
1
2
3
4
N–2
N –1
N
1
N+1
N
N–1
N–2
4
3
2
1
0
DCLKR
FSR
DIN
Receive Time Slot
tsu(FSR)
th(FSR)
See Note B
th(DIN)
tsu(DIN)
tc(DCLKR)
See Note A
20%
80%
See Note C
80%
20%
NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations).
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.
Figure 4. Variable-Data-Rate, Receive Side Timing Diagram
4
N
N–1
N–2
3
2
1
N+1
N
N–1
N–2
4
3
2
1
0
DCLKX
FSX
DOUT
tsu(FSX)
Transmit Time Slot
th(FSX)
See Note B
tpd8
tpd7
tpd6
See Note A
tc(DCLKR)
20%
80%
20%
80%
See Note C
80%
NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low without data repetition.
C. Transitions are measured at 50%.
Figure 5. Variable-Data-Rate, Transmit Side Timing Diagram
APPLICATION INFORMATION
output gain set design considerations (see Figure 6)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:
VO+ at EARA
VO– at EARB
VOD = VO+ – VO– (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 k
and less than 100 k for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
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