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| 型号： | TCS3415FN |
| 厂商： | AMS-TAOS USA Inc |
| 文件页数： | 20/41页 |
| 文件大小： | 0K |
| 描述： | IC COLOR SENSOR DGTL PROGR 6-DFN |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TCS3415-FNDKR TCS3415-FNDKR-ND TCS3415FNDKR |
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TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A ? APRIL 2011
Gain Register (07h)
The Gain register provides a common gain control adjustment for all four parallel ADC output channels. Two
gain bits [5:4] in the Gain Register allow the relative gain to be adjusted from 1 × to 64 × in 4 × increments. The
advantage of the gain adjust is to extend the dynamic range of the light input up to a factor of 64 × before analog
or digital saturation occurs. If analog saturation has occurred, lowering the gain sensitivity will likely prevent
analog saturation especially when the integration time is relatively short. For longer integration times, the 16-bit
output could be in digital saturation (64K). If lowering the gain to 1 × does not prevent digital saturation from
occurring, the use of PRESCALER can be useful.
The PRESCALER is 3 bits [2:0] in the gain register that divides down the output count (i.e. shifts the LSB of the
count value to the right). The PRESCALER adjustment range is divide by 1 to 64 in multiples of 2.
The most sensitive gain setting of the device would be when GAIN is set to 11b (64 × ), and PRESCALER is set
to 000b (divide by 1). The least sensitive part setting would be GAIN 00 (1 × ) and PRESCALER 110 (divide by
64). If the part continues to be in digital saturation at the least sensitive setting, the integration time can be
lowered (see Timing Register section).
Table 9. Gain Register
07h
7
Resv
6
Resv
5
GAIN
4
3
Resv
2
1
PRESCALER
0
GAIN
Reset Value:
0
0
0
0
0
0
0
0
FIELD
Resv
BITS
7:6
DESCRIPTION
Reserved. Write as 0.
Analog Gain Control. This field switches the common analog gain of the four ADC channels. Four gain
modes are provided:
FIELD VALUE
GAIN
GAIN
Resv
5:4
3
00
01
10
11
Reserved. Write as 0.
1 ×
4 ×
16 ×
64 ×
Prescaler. This field controls a 6-bit digital prescaler and divider. The prescaler reduces the sensitivity
of each ADC integrator as shown in the table below:
FIELD VALUE
000
001
Divide by 1.
Divide by 2.
PRESCALER MODE
PRESCALER
2:0
010
011
100
101
110
111
Divide by 4.
Divide by 8.
Divide by 16.
Divide by 32.
Divide by 64.
Not used.
The LUMENOLOGY r Company
r
www.taosinc.com
r
Copyright E 2011, TAOS Inc.
19
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相关代理商/技术参数 |
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