参数资料
| 型号： | TDA21301 |
| 厂商： | Infineon Technologies |
| 文件页数： | 15/25页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM MULTI CPU TSSOP-28 |
| 产品变化通告： | Product Discontinuation 30/Jul/2007 |
| 标准包装： | 2,500 |
| 应用： | PWM控制器，CPU 内核 |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 4 |
| 输出电压： | 0.8375 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | P-TSSOP-28 |
| 包装： | 带卷 (TR) |
| 其它名称： | SP000013699 TDA21301T |
order to eliminate this hump, a resistor placed at CSN to GND has been introduced here. The value of
this resistor can be calculated by the formula below.
≥ ? R CSN2 ≤
V CSN
R CSN2
I L × DCR V CSN × R CSN
R CSN I L × DCR
DAC Offset Voltage & Droop Setting
×
The DAC offset voltage is set by compensation network & external resistor at VOSS pin by
1.65V R FB
R VOSS 4
The summed current signals from power channels are injected to ADJ pin to establish the droop
∑ n = 1 2I xn . The DAC output voltage decreased by V
voltage, V ADJ =R ADJ ×
n = 4
ADJ
to generate the V CORE
load droop.
PGOOD VCC DVD IMAX
Offset Voltage = - 0,25 I VOSS x R FB
OVP
+
Setting
Control
+
Setting ( 0,25I VOSS x R FB )
V ADJ = I SUM x R ADJ
+
+
VID0
VID1
VID2
VID3
VID4
VID125
VOSS
R VOSS
Droop Voltage = I SUM x R ADJ
V DAC
VID DAC
& Step
PG
Setting
+
I
I VOSS = 1,65V/R VOSS Error
Amplifier
Power On
Reset
I
I
Offset V DAC - I SUM x R ADJ –
INH
OCP
Setting
RT
Oscillatior &
Sawtooth
+ +
+
+
+ +
Current
Correction
+
I
+
I
+
I
+
I
Phase Control
INH
PWM Logic
PWM CMP
INH
PWM Logic
PWM CMP
INH
PWM Logic
PWM CMP
INH
PWM Logic
PWM CMP
PWM1
PWM2
PWM3
PWM4
CSP1
CSP2
CSP3
CSP4
R SGND
SGND
CSN
PGND
0,25 I VOSS
Soft
Start
SUM/M
V CORE
R FB
FB
COMP
SS
ADJ
R ADJ
I SUM = 2(I X1 +I X2 +I X3 +I X4 )
Protection and SS Function
For OVP, the TDA21301 detects the V CORE by FB pin voltage that is the inverting input of the error
amplifier. This is to eliminate the delay caused by the compensation network for faster and more
accurate detection. The trip point of OVP is 140% of the normal V CORE voltage level. The PWM outputs
are pulled low to turn on the Sync FET and to turn off the control FET while OVP is detected. The OVP
latch can only be reset by either VCC or DVD. The PGOOD trip point is set at the 92% of the normal
V CORE voltage level. The open drain PGOOD pin shall be pulled low while V CORE is lower than this trip
point. During the VID on the fly condition, there is nothing able to change the status of the PGOOD.
CoreControl TM
Page 15 of 25
DS-CoreControl-TDA21301
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TDA21301ZT | 制造商:Infineon Technologies AG 功能描述:Multi Phase PWM Controller 28-Pin TSSOP T/R |
| TDA21302 | 功能描述:IC CTRLR PWM MULTI CPU PDSO-32 RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| TDA2140 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:LINEAR INTEGRATED CIRCUIT |
| TDA2148 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:AM AMPLIFIER FOR FRENCH SOUND IF STANDARD |
| TDA2151 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:LINEAR INTEGRATED CIRCUIT |
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