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参数资料
| 型号： | TDA7326 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 140 MHz, PDIP16 |
| 封装： | DIP-16 |
| 文件页数： | 11/16页 |
| 文件大小： | 1133K |
| 代理商： | TDA7326 |
ELECTRICAL CHARACTERISTICS (continued)
LOOP FILTER OUTPUT (LPOUT = PIN 14)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
vOL
Output Voltage Low
ILOAD = 0.2mA VDD2; = 10V
0.5
0.8
V
VOH
Output Voltage High
-ILOAD = 0.2mA VDD2; = 10V
9
9.5
V
CHARGE PUMP CURRENT GENERATION (LPIN1, LPIN2 = PIN 15, 16)
Isi
Sink Current LPIN1,2
CURR1 = 0, CURR2 = 0
2
5
7
A
CURR1 = 0, CURR2 = 1
120
200
280
A
CURR1 = 1, CURR2 = 1
180
300
420
A
CURR1 = 1, CURR2 = 0
370
500
630
A
-Iso
Source Current LPIN1,2
CURR1 = 0, CURR2 = 0
2
5
7
A
CURR1 = 0, CURR2 = 1
120
200
280
A
CURR1 = 1, CURR2 = 1
180
300
420
A
CURR1 = 1, CURR2 = 0
370
500
630
A
DOUT1 OPENDRAIN OUTPUT(PIN 9)
vOL
Output Voltage Low
ILOAD = 1mA
0.2
0.5
V
BUS INTERFACE
-IIL
Input Leakage Current
VIN = VSS
-1
0.1
1
A
IIH
Input Leakage Current
VIN = VSS
-1
0.1
1
A
vIH
Input Voltage High
Leading edge
3.4
4.0
V
VIL
Input Voltage Low
Leading edge
1.0
1.6
V
BUS INTERFACE, WAITING TIME (see fig. 5) The Data is Acquired at the High
→ Low Clock Transition
t1
CLK Low to DLEN L
→ H0.2
s
t3
DATA Transition to CLK H
→ L0.1
s
t5
CLK H
→ L to DATA Transition
0.4
s
BUS INTERFACE, DATA REPETITION TIME (see fig. 5)
tr1
Release Time Between 2 bytes,
except byte 4
5
s
tr2
Release Time after the
transmission of byte 4
FM mode
180
s
AM mode
2
ms
BUS INTERFACE, SETUP TIME (see fig. 5)
t2
DLEN High to CLK L
→ H0.1
s
BUS INTERFACE, HOLD TIME (see fig. 5)
t4
DATA Transition to CKL L
→ H0
s
t6
CLK H
→ L to DLEN H → L
0.4
s
fCLK
CLK Frequency
500
KHz
Duty Cycle
50
%
tpl
Clock Pulse Low
1
s
tph
Clock Pulse High
1
s
TDA7326
4/16
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