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参数资料
| 型号： | TDA7427AD1TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 200 MHz, PDSO28 |
| 封装： | SO-28 |
| 文件页数： | 3/22页 |
| 文件大小： | 444K |
| 代理商： | TDA7427AD1TR |
I
2C BUS INTERFACE DESCRIPTION
The TDA7427A supports the I
2C bus protocol.
This protocol defines any device that sends data
into the bus as a transmitter and the receiving de-
vice as the receiver. The device that controls the
transfer is the master and the device being con-
trolled is the slave. The master always initiates
data transfer and provides the clock to transmit or
receive operations.
Data Transition
Data transition on the SDA line must only occur
when the clock SCL is low. SDA transitions while
SCL is high will be interpreted as START or
STOP condition.
Start Condition
A start condition is defined by a HIGH to LOW
transition of the SDA line while SCL is at a stable
HIGH level. This START condition must precede
any command and initiate a data transfer onto the
bus. The TDA7427A continuously monitors the
SDA and SCL lines for a valid START and will not
response to any command if this condition has
not been met.
Stop Condition
A STOP condition is defined by a LOW to HIGH
transition of the SDA while the SCL line is at a stable
HIGH level. This condition terminate the communica-
tion between the devices and forces the bus interface
of the TDA7427A into the initial condition.
Acknowledge
Indicates a successful data transfer. The transmit-
ter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the
SDA line to LOW level to indicate it has receive
the eight bits of data correctly.
Data transfer
During data transfer the TDA7427A samples the
SDA line on the leading edge of the SCL clock.
Therefore, for proper device operation the SDA
line must be stable during the SCL LOW to HIGH
transition.
Device Addressing
To start the communication between two devices,
the bus master must initiate a start instruction se-
quence, followed by an eight bit word correspond-
ing to the address of the device it is addressing.
The most significant 6 bits of the slave address
are the device type identifier.
The TDA7427A frequency synthesizer device
type is fixed as "110001"
The next significant bit is used to address a par-
ticular device of the previous defined type con-
nected to the bus. The state of the hardwired A0
pin defines the state of this address bit. So up to
two devices could be connected on the same bus.
The last bit of the instruction defines the type of
operation to be performed:
- When set to "1", a read operation is selected
- When set to "0", a write operation is selected
The chip selection is accomplished by setting the
bit of the chip address to the corresponding status
of the A0 input.
All TDA7427A connected to the bus will compare
their own hardwired address with the slave ad-
10
F
100nF
VDD2
15
VDD1
19
+10V
+5V
AM-FM
IF
IF_FM
11
IF_AM
10
10nF
TDA7427
13
12
7
14
INLOCK/DOUT1
SSTOP
DOUT3
HFREF
8
9
VDD1
SCL
SDA
CONTROLLER
56
OSCIN
OSCOUT
100nF
4
VREF
4MHz
3
6.8nF
100K
68nF
27K
6.8nF
1nF
1
2
15K
AM VCO
FM VCO
16
20
17
10nF
1nF
Utun
AM_IN
FM_IN
LPOUT
LP_FM
LP_HC
LP_AM
D95AU379B
10nF
10
F
3.9K
100nF
820
3.3nF
FM:50KHz
AM:1KHz
Figure 6. Application with two loop filters
TDA7427A
11/21
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