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参数资料
| 型号： | TDA8315T/N3 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 颜色信号转换 |
| 英文描述： | COLOR SIGNAL DECODER, PDSO24 |
| 封装： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24 |
| 文件页数： | 3/18页 |
| 文件大小： | 104K |
| 代理商： | TDA8315T/N3 |
September 1994
11
Philips Semiconductors
Preliminary specication
Integrated NTSC decoder
and sync processor
TDA8315T
13. The horizontal output pulses are obtained from the horizontal oscillator by a pulse shaper. The width of the output
pulse is approximately 5.4
s and the rising edge of the pulse symmetrically coincides with the start of the sync pulse
at the input.
14. The vertical output pulses are generated by a divider circuit. The vertical output pulse has a delay of 37.5
s with
respect to the start of the vertical sync pulse at the input. This is caused by the clock frequency of the divider being
twice the horizontal frequency.
This divider circuit has 2 modes of operation:
Search mode (large window).
This mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number
of lines per frame outside the range is between 261 and 264). In the search mode the divider can be triggered
between line 244 and line 288 (approximately 54 to 64.5 Hz).
Standard mode (narrow window).
This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the output pulse is generated at the end
of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search
window when, for 6 successive vertical periods, no sync pulses are found within the window. When no input signal
is available the divider generates output pulses with a timing of 262.5 lines (standard 60 Hz signal).
Table 1 Output current of phase detector.
Note
1. Vertical retrace.
QUALITY SPECIFICATION
Quality level in accordance with SNW-FQ-611-part E.
Notes
1. All pins are protected against ESD by means of internal clamping diodes.
2. Range A is for Human body model.
3. Range B is for machine model.
Latch up
All pins meet the specification:
Itrigger ≥ 100 mA or ≥ 1.5 VDDmax
Itrigger ≤100 mA or ≤0.5 VDDmax.
CURRENT PHASE DETECTOR DURING
SCAN (
A)
VERTICAL RETRACE (
A)
GATED YES/NO
Weak signal and synchronized
30
YES (5.7
s)
Strong signal and synchronized
180
270
YES (12
s)(1)
Not synchronized
180
270
NO
SYMBOL
PARAMETER
RANGE A(2)
RANGE B(3)
UNIT
ESD
protection circuit specication (note 1)
>2000
>200
V
100
200
pF
1500
0
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