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参数资料
| 型号： | TFDT6502E-TR3 |
| 厂商： | VISHAY SEMICONDUCTORS |
| 元件分类： | 其它接口 |
| 英文描述： | SPECIALTY INTERFACE CIRCUIT, XMA8 |
| 封装： | 13 X 7.60 X 5.95 MM, TOP VIEW-8 |
| 文件页数： | 15/18页 |
| 文件大小： | 690K |
| 代理商： | TFDT6502E-TR3 |
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Rev. B1.6, 02–Nov–00
6
www.vishay.com
Document Number 82526
Optoelectronic Characteristics
Tamb = 25_C, VCC = 2.6 V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Receiver
Minimum Detection
Threshold Irradiance,
SIR Mode
TFDS6502E/ TFDT6502E
9.6 kbit/s to 115.2 kbit/s
l = 850 nm to 900 nm
Ee
20
35
mW/m2
SIR Mode
TFDU6102E, TFDS6402
9.6 kbit/s to 115.2 kbit/s
l = 850 nm to 900 nm
Ee
25
40
mW/m2
Minimum Detection
Threshold Irradiance,
MIR Mode
TFDS6502E/ TFDT6502E
1.152 Mbit/s
l = 850 nm to 900 nm
Ee
50
mW/m2
MIR Mode
TFDU6102E, TFDS6402
1.152 Mbit/s
l = 850 nm to 900 nm
Ee
65
mW/m2
Minimum Detection
Threshold Irradiance,
FIR Mode
TFDS6502E/ TFDT6502E
4.0 Mbit/s
l = 850 nm to 900 nm
Ee
65
100
mW/m2
FIR Mode
TFDU6102E, TFDS6402
4.0 Mbit/s
l = 850 nm to 900 nm
Ee
85
100
mW/m2
Maximum Detection
Threshold Irradiance
l = 850 nm to 900 nm
Ee
5
10
kW/m2
Logic LOW Receiver
Input Irradiance
Ee
4
mW/m2
Rise Time of Output
Signal––,,,,klll
10% to 90%, @2.2 k
, 15 pF
tr (Rxd)
10
40
ns
Fall Time of Output
Signal
90% to 10%, @2.2 k
, 15 pF
tf (Rxd)
10
40
ns
Rxd Pulse Width of
Input pulse length 20
s, 9.6 kbit/s
tPW
1.2
10
20
s
Rxd Pulse Width of
Output Signal, 50%
SIR Mode
Input pulse length 1.41
ms,
115.2 kbit/s
tPW
1.2
1/2 bit
length
s
Rxd Pulse Width of
Output Signal, 50%
MIR Mode
Input pulse length 217 ns,
1.152 Mbit/s
tPW
110
260
ns
Rxd Pulse Width of
Output Signal 50%
Input pulse length 125 ns, 4.0 Mbit/s
tPW
100
160
ns
Output Signal, 50%
FIR Mode
Input pulse length 250 ns, 4.0 Mbit/s
tPW
200
290
ns
Stochastic Jitter,
Leading Edge,
FIR Mode
Input Irradiance = 100 mW/m2,
4.0 Mbit/s
±10
ns
Latency
tL
120
300
s
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