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参数资料
| 型号： | TH7422BVWJNGS |
| 厂商： | ATMEL CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC84 |
| 封装： | WINDOWED, CERAMIC, J LEAD PACKAGE-84 |
| 文件页数： | 7/20页 |
| 文件大小： | 1116K |
| 代理商： | TH7422BVWJNGS |
APPLICATION INFORMATION
- Preload generation
Preload is fed up when
ΦPL is at low level. This process needs few time to be completed(>35 ns). Then skimming is nee-
ded to calibrate Qb. This step needs as much as possible time. Therefore it is recommended to activate
ΦPL as soon as
ΦL2 is at low level, in order to spend most of ΦL2 low level duration for skimming.
Qb depends on (VGL2 -VGL1 ) difference, thus noise on Qb may result from differential fluctuations between VGL1 and VGL2.
It is therefore recommended to get VGL1 and VGL2 biases on each side (Odd or Even) from the same power supply line.
- Preload level adjustment
Preload level must be chosen so as to covered both expected maximum signal and dark current resulting signal. It must be noti-
ced that the “Vidicon mode” implies output signal has the largest amplitude in darkness (since most of Qb is to be readout).
Since output signal treatment difficulty may arise from its large amplitude it is better to reduce as much as possible its dyna-
mic, thus to reduce preload level to the minimum required.
From Figure 6, dark voltage can be deduced, photosignal is computed from Figures3&4and application data (light flux, in-
tegration time). Preload must be 200 mV in excess to dark voltage and maximum photosignal sum. Preload can be adjusted
with (VGL2 -VGL1 ) biases, as indicated in Figure 7, however it is recommended to act first on VGL2. Direct read out of pre-
load level is possible in forcing
ΦX at low level avoiding lateral transfer and photodiode read out.
TH7422B maximum preload is about 2.5 V (corresponding to 107 electrons).
- Photodiode information collection
As explained this operation needs two steps :
a). Qb injection into input nodes.
b). Skimming back into main register of extra charges.
Step a) needs at least 1 s to be completed (TX1). However, step b) is a longer process, which duration influences lateral
transfer efficiency. It has been measured that 20 s is needed for less than1%transfer non efficiency which raises to 2 %
for 4 s skimming time (TX2).
Thus it is recommended to allow as long as possible skimming time, compatible with application requirement.
- Output signal format
Figures 1 and 2 give details on output signal. Each reset (
ΦR) pulse pulls up the output at reset level related to VDR bias.
Using typical biases, reset level reaches about 12 volts with respect to Vss. Notice that
ΦR must be pulsed only when ΦL2
is at high level.
Just after reset pulse, output level is stabilizing to a steady level called “floating diode level”. This level is the very reset level
to be taken into account for useful signal amplitude measurement. It is about 200 mV lower than reset level.
Then on
ΦL2 falling edge, charges coming from main register last stage arrive. Consequently, output signal drops down.
The new steady level reached, counted from “floating diode” level represents the useful information - Uos -
Uos amplitude is maximum when no lateral transfer has occurred, since it represents preload level. In darkness, after pho-
todiode read out (lateral transfer) Uos is reduced by dark voltage signal. Under illumination Uos is still smaller until satura-
tion occurs (whole preload consumption), in this situation “floating diode” level is maintained until next pixel readout.
- Read enable operation
RE input simplifies device operation since it allows to use continuous
ΦL2 clocks. However, one can force RE at high level
and generate external
ΦL2 interruption during ΦX transfer. In this case, first pixel data will be read out at first falling edge of
ΦL2. After 150 ΦL2 periods all pixel data will have been read out, on 151st ΦL2 period, output will be unused preload and so
on until next
ΦX cycle.
When using RE input, it must be noticed that RE duration must at least allow 150 main register transfers (
ΦL2 periods) in
order to guaranty that all main register stages contain a preload (Qb) before next
ΦX cycle. Otherwise all photodiodes will
not be properly reset at next
ΦX cycle.
When RE is low, output signal is continuously at floating diode level, with
ΦR transparencies.
- Interlacing odd even
As odd and even sides are fully separated, it is possible to drive odd and even side with 180° phase shifted
ΦL1 and ΦL2
(
ΦPL , ΦR with same phase with respect to their ΦL2), ΦX being identicals.In this manner Odd output signals will be delayed
by half a Tck period with respect to Even outputs allowing, after common sampling, natural multiplexing and double pixel
data rate. This opportunity is presented in application hints (Figures 10 to 12).
- Mechanical mounting
Accurate mechanical references are provided in N and P subvariant packages (see ordering information and outline drawings).
If optics are mechanically referred to these packages rear face, no tuning strategy could be implemented for scale manufacturing.
15/20
TH7422B
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相关代理商/技术参数 |
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| TH7813A | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:50 MHz 1024/2048 Linear CCDs |
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