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参数资料
| 型号： | TH7422BVWORGB/T |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC84 |
| 封装： | CERAMIC, J LEAD PACKAGE-84 |
| 文件页数： | 15/20页 |
| 文件大小： | 1116K |
| 代理商： | TH7422BVWORGB/T |
TABLE 2 - CONNECTION DIAGRAMS
Pin n°
EVEN
Mo-
dule
#
Sym-
bol
Designation
Pin n°
ODD
Mo-
dule
#
Sym-
bol
Designation
1...2
NC
Not connected
44...51
TC+
Thermoelectric cooler (positive node)
see notes (2) (3)
3...6
TS
Temperature sensor see note (3)
52...55
NC
Not connected
7...9
NC
Not connected
56
O
VG1
Lateral skimming gate bias
10
DNC
Do not connect see note (4)
57
O
φX
Photodiode lateral transfer clock
11...14
NC
Not connected
58
O
φPL
Electrical injection clock
15
E
VDD
Output amplifier drain & RE
59
O
VGL1
Preload skimming gate bias
16
E
VOS
Video output signal (pixels 0-298)
60
O
VGL2
Preload storage gate bias
17
E
GND
Video ground
61
O
φL2
Shift register clock 2 (gated by RE)
18
E
VSS
CCD substrate bias (phases return)
62
O
RE
Read enable control signal
(pixels 1-299)
19
E
φR
CCD reset clock
63
O
φL1
Shift register clock 1
20
E
VDR
Reset bias
64
O
VN
Photodiode substrate bias
see note (1)
21
E
VGS
Output gate bias
65
O
VGS
Output gate bias
22
E
VN
Photodiode substrate bias see
note (1)
66
O
VDR
Reset bias
23
E
φL1
Shift register clock 1
67
O
φR
CCD reset clock
24
E
RE
Read enable control signal
(pixels 0-298)
68
O
VSS
CCD substrate bias (phases return)
25
E
φL2
Shift register clock 2 (gated by RE)
69
O
GND
Video ground
26
E
VGL2
Preload storage gate bias
70
O
VOS
Video output signal (pixels 1-299)
27
E
VGL1
Preload skimming gate bias
71
O
VDD
Output amplifier drain & RE supplies
28
E
φPL
Electrical injection clock
72...75
NC
Not connected
29
E
φX
Photodiode lateral transfer clock
76
DNC
Do not connect see note (4)
30
E
VG1
Lateral skimming gate bias
77...79
NC
Not connected
31...34
NC
Not connected
80...83
TS
Temperature sensor see note (3)
35...42
TC-
Thermoelectric cooler (negative node)
see notes (2) (3)
84
NC
Not connected
43
NC
Not connected
Note : 1 Pin 22 and 64 are internally connected together
Note : 2 In each group every pins must be connected and tied together in order to lower pin current density
Note : 3 Not connected on non cooled package
Note : 4 DNC (Do Not Connect). Pins which are internally connected and must not be used.
4/20
TH7422B
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