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参数资料
| 型号： | THS10082CDAG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封装： | GREEN, PLASTIC, TSSOP-32 |
| 文件页数： | 32/37页 |
| 文件大小： | 375K |
| 代理商： | THS10082CDAG4 |
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THS10082
SLAS254B MAY 2002 REVISED NOVEMBER 2002
www.ti.com
4
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 8 MHz, fI = 2 MHz at 1 dB (unless otherwise noted)
AC SPECIFICATIONS, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SINAD
Signal-to-noise ratio + distortion
Differential mode
56
59
dB
SINAD
Signal-to-noise ratio + distortion
Single-ended mode(1)
55
58
dB
SNR
Signal-to-noise ratio
Differential mode
59
61
dB
SNR
Signal-to-noise ratio
Single-ended mode(1)
60
dB
THD
Total harmonic distortion
Differential mode
67
61
dB
THD
Total harmonic distortion
Single-ended mode
63
dB
ENOB
Effective number of bits
Differential mode
9
9.5
Bits
ENOB
Effective number of bits
Single-ended mode(1)
9.35
Bits
SFDR
Spurious free dynamic range
Differential mode
61
65
dB
SFDR
Spurious free dynamic range
Single-ended mode
64
dB
Analog Input
Full-power bandwidth with a source impedance of 150
in
differential configuration.
Full-scale sinewave, 3 dB
96
MHz
Full-power bandwidth with a source impedance of 150
in
single-ended configuration.
Full-scale sinewave, 3 dB
54
MHz
Small-signal bandwidth with a source impedance of 150
in
differential configuration.
100-mVpp sinewave, 3 dB
96
MHz
Small-signal bandwidth with a source impedance of 150
in
single-ended configuration.
100-mVpp sinewave, 3 dB
54
MHz
(1) The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling
clock.
TIMING REQUIREMENTS(1)
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(DATA_AV)
Delay time
5
ns
td(o)
Delay time
5
ns
tpipe
Latency
5
CONV
CLK
(1) See Figure 27.
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
Clock cycle of the internal clock oscillator
117
125
133
ns
tw1
Pulse duration, CONVST
One analog input
1.5
×tc
ns
tw1
Pulse duration, CONVST
Two analog inputs
2.5
×tc
ns
td(A)
Aperture time
1
ns
t2
Delay time between consecutive start of
One analog input
2
×tc
ns
t2
Delay time between consecutive start of
single conversion
Two analog inputs
3
×tc
ns
One analog input, TL = 1
6.5
×tc+15
ns
Two analog inputs, TL = 2
7.5
×tc+15
ns
One analog input, TL = 4
3
×t2 +6.5×tc+15
ns
td(DATA_AV)
Delay time, DATA_AV becomes active for the
Two analog inputs, TL = 4
t2 +7.5×tc+15
ns
td(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 1
One analog input, TL = 8
7
×t2 +6.5×tc+15
ns
trigger level condition: TRIG0 = 1, TRIG1 = 1
Two analog inputs, TL = 8
3
×t2 +7.5×tc+15
ns
One analog input, TL = 14
13
×t2 +6.5×tc+15
ns
Two analog inputs, TL = 12
13
×t2 +6.5×tc+15
ns
(1) See Figure 26.
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