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| 型号： | THS10082IDAR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封装： | GREEN, PLASTIC, TSSOP-32 |
| 文件页数： | 20/37页 |
| 文件大小： | 350K |
| 代理商： | THS10082IDAR |
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THS10082
SLAS254B MAY 2002 REVISED NOVEMBER 2002
www.ti.com
27
DATA_AV Type
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1
determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of
DATA_AV. This is shown in Table 14.
Table 14. DATA_AV Type
BIT 5
DATA_P
BIT 4
DATA_T
DATA_AV TYPE
0
Active low level
0
1
Active low pulse
1
0
Active high level
1
Active high pulse
The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive dependent of the DATA_T
selection (pulse or level).
If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge of
READ). The trigger condition is checked again after TL reads. For single conversion mode, the DATA_AV type should be
programmed to active level mode.
If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous
conversion mode.
Read Timing (Using R/W, CS0-Controlled)
Figure 36 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.
The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0, CS1, and R/W which becomes valid.
90%
10%
tw(CS)
tsu(R/W)
th(R/W)
ta
th
td(CSDAV)
CS0
CS1
R/W
RD
D(09)
DATA_AV
Figure 36. Read Timing Diagram Using R/W (CS0-controlled)
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| THS1009CDAG4 | 制造商:TI 制造商全称:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
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