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| 型号： | THS1009CDA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封装： | PLASTIC, TSSOP-32 |
| 文件页数： | 17/31页 |
| 文件大小： | 289K |
| 代理商： | THS1009CDA |
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THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
24
Read Timing (using R/W, CS0-controlled)
Figure 31 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data should be done with
a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 31.
10%
90%
10%
tsu(CONV_CLKL–CSOL)
tsu(CSOH–CONV_CLKL)
tw(CS)
tsu(R/W)
th(R/W)
ta
th
CONV_CLK
CS0
CS1
R/W
RD
D(0–11)
Figure 31. Read Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CONV_CLKL–CSOL)
Setup time, CONV_CLK low before CS valid
10
ns
tsu(CSOH–CONV_CLKL)
Setup time, CS invalid to CONV_CLK low
20
ns
tsu(R/W)
Setup time, R/W high to last CS valid
0
ns
ta
Access time, last CS valid to data valid
0
10
ns
th
Hold time, first CS invalid to data invalid
0
5
ns
th(R/W)
Hold time, first external CS invalid to R/W change
5
ns
tw(CS)
Pulse duration, CS active
10
ns
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相关代理商/技术参数 |
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| THS1009CDAG4 | 制造商:TI 制造商全称:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
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| THS1009IDA | 功能描述:模数转换器 - ADC 10 BIT QUAD ADC w/o RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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