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参数资料
| 型号： | THS1215IPW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, TSSOP-28 |
| 文件页数： | 3/22页 |
| 文件大小： | 391K |
| 代理商： | THS1215IPW |
www.ti.com
PRINCIPLES OF OPERATION
ANALOG INPUT
AIN
0
4095
2V
MODE 2, CON[1:0] = 10
OUTPUT
CODE
AIN
0
4095
1V
MODE 1, CON[1:0] = 01
OUTPUT
CODE
AIN+
THS1215
SLAS292A – MARCH 2001 – REVISED MARCH 2004
The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC CORE, where
the process of analog-to-digital conversion is performed against ADC reference voltages, VREFT and VREFB.
Connecting the EXTREF pin to one of two voltages, DGND or DVDD selects one of the two configurations of ADC
reference generation. The ADC reference voltages come from either the internal reference buffer or completely
external sources. Connect EXTREF to DGND for internal reference generation or to DVDD for external reference
generation.
CON0 and CON1 as described below, select the input configuration mode or place the device in power-down
state. The ADC core drives out through output buffers to the data pins D0 to D11. The output buffers can be
disabled by the OE pin.
A single, sample-rate clock (15 MHz maximum) is required at pin CLK. The analog input signal is sampled on the
rising edge of CLK, and corresponding data is output after the fifth following rising edge.
The THS1215 can operate in differential Mode 1 or differential Mode 2, controlled by the configuration pins
CON0 and CON1 as shown in Table 1. Mode 0 places the THS1215 in power-down or standby state for reduced
power consumption.
Table 1. Input Modes of Operation
MODE
CON1
CON0
MODE OF OPERATION
0
Device powered down
1
0
1
Differential mode
× 1
2
1
0
Differential mode
× 0.5
3
1
Not used
Modes 1 and 2 are shown in Figure 14.
Figure 14. Input Mode Configurations
The gain of the sample and hold changes with the CON1 and the CON0 inputs. Table 2 shows the gain of the
sample and hold and the levels applied at the AIN+ and AIN– analog inputs for Mode 1 and Mode 2. The
common mode level for the two analog inputs is at AVDD/2.
Table 2. Input Mode Switching
(AIN+) – (AIN-)
MODE
CON1
CON0
S/H GAIN
MIN
MAX
1
0
1
–1 V
1 V
×1
2
1
0
-2 V
2 V
×0.5
11
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