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参数资料
| 型号： | THS1230CDWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, SOIC-28 |
| 文件页数： | 23/25页 |
| 文件大小： | 854K |
| 代理商： | THS1230CDWRG4 |
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ELECTRICAL CHARACTERISTICS (CONTINUED)
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
over recommended operating conditions (AV
DD = DVDD = 3.3 V, fs = 30 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, T
min to Tmax) (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
DC ACCURACY (LINEARITY)
Number of missing codes
All modes
0
codes
DNL
Differential nonlinearity
All modes
±0.4
±1
LSB
INL
Integral nonlinearity
All modes
–2.5
±1.2
2
LSB
Offset error
All modes
0.7
1.2
%FSR
Gain error
All modes
1.1
3.5
%FSR
DYNAMIC PERFORMANCE(1)
fi = 3.58 MHz
10.9
ENOB
Effective number of bits
fi = 10 MHz
10.4
10.6
Bits
fi = 15 MHz
10.4
fi = 3.58 MHz
–76
THD
Total harmonic distortion
fi = 10 MHz
–74
–65
dB
fi = 15 MHz
–72.5
fi = 3.58 MHz
68
SNR
Signal-to-noise ratio
fi = 10 MHz
64.5
65.6
dB
fi = 15 MHz
64.6
fi = 3.58 MHz
67.4
SINAD
Signal-to-noise + distortion
fi = 10 MHz
64
65
dB
fi = 15 MHz
64.5
fi = 3.58 MHz
78.1
SFDR
Spurious free dynamic range
fi = 10 MHz
67
74
dB
fi = 15 MHz
72
Analog input bandwidth
180
MHz
Differential phase, DP
0.12
degree
G(diff)
Differential gain
0.01%
TIMING (all supplies = 3.3 V)
fCLK
Clock frequency(2)
5
30
MHz
Clock duty cycle
45%
50%
55%
td(O)
Output delay time
7
19
ns
td(PZ)
Delay time, output disable to Hi-Z output
3.2
ns
td(EN)
Delay time, output enable to output valid
5
19
ns
Latency
5
cycles
(1)
Input amplitudes for all single tone dynamic tests are at –1 dBFS, all supplies = 3.3 V.
(2)
The clock frequency may be extended to 5 MHz without degradation in specified performance.
7
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